- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄375011 > XCR3128XL (Xilinx, Inc.) CoolRunner XPLA3 CPLD(CoolRunner XPLA3復(fù)雜可編程邏輯器件) PDF資料下載
參數(shù)資料
| 型號(hào)： | XCR3128XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | CoolRunner XPLA3 CPLD(CoolRunner XPLA3復(fù)雜可編程邏輯器件) |
| 中文描述： | 的CoolRunner CPLD的XPLA3（的CoolRunner XPLA3復(fù)雜可編程邏輯器件） |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 109K |
| 代理商： | XCR3128XL |
R
Macrocell Architecture
Figure 5
shows the architecture of the macrocell used in the
CoolRunner XPLA3. Any macrocell can be reset or preset
on power-up. Each macrocell register can be configured as
a D-, T-, or Latch-type flip-flop, or bypassed if the macrocell
is required as a combinatorial logic function.
Each of these flip-flops can be clocked from any one of eight
sources or their complements. There are two global syn-
chronous clocks that are selected from the four external
clock pins. There is one universal clock signal. The clock
input signals CT[4:7] (Local Control Terms) can be individu-
ally configured as either a PRODUCT term or SUM term
equation created from the 36 signals available inside the
function block.
There are two muxed paths to the ZIA. One mux selects
from either the output of the VFM or the output of the regis-
ter. The other mux selects from the output of the register or
from the I/O pad of the macrocell. When the I/O pin is used
as an output, the output buffer is enabled, and the macrocell
feedback path can be used to feed back the logic imple-
mented in the macrocell. When an I/O pin is used as an
input, the output buffer will be 3-stated and the input signal
will be fed into the ZIA via the I/O feedback path. The logic
Figure 3:
Xilinx XPLA3 Function Block Architecture
Figure 4:
Variable Function Multiplexer
Foldback NAND
(P
T
[8:15])
(P
T
[0:47])
(P
T
0)
(P
T
7)
(P
T
[32:47])
(P
T
16)
(P
T
[0:47])
(P
T
31)
To Local Control Term (LCT0)
To Universal Control Term (UCT) Mux
To Local Control Term (LCT7)
P-term Clocks
8
Product
Term
Array
36 x 48
ZIA
36
VFM
Macrocell 1
D
Q
I/O1
ZIA
ZIA
1
1
1
48
D
Q
ZIA
ZIA
I/O16
VFM
Macrocell 16
1
48
DS012_02_101200
From PLA OR Term
To Combinatorial Path
and Register Input
From P-term
DS012_03_121699
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCR3256XL-12TQ144I | Connector |
| XCR3256XL-7CS280C | 256 Macrocell CPLD |
| XCR3256XL-7CS280I | Connector |
| XCR3256XL-7FT256C | 256 Macrocell CPLD |
| XCR3256XL-7FT256I | 256 Macrocell CPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3128XL-10CS144C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144C IC SYSTEM GATE |
| XCR3128XL-10CS144I | 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144I IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CS144I-STI | 制造商:Xilinx 功能描述: |
| XCR3128XL-10CSG144C | 制造商:Xilinx 功能描述: 制造商:Xilinx 功能描述:XLXXCR3128XL-10CSG144C IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CSG144I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。