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參數(shù)資料
| 型號(hào)： | XCR3128XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | CoolRunner XPLA3 CPLD(CoolRunner XPLA3復(fù)雜可編程邏輯器件) |
| 中文描述： | 的CoolRunner CPLD的XPLA3（的CoolRunner XPLA3復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 109K |
| 代理商： | XCR3128XL |
Table 3:
XPLA3 Low-level JTAG Boundary-scan Commands
Instruction
(Instruction Code)
Register Used
Description
Sample/Preload
(00010)
Boundary-scan Register
The mandatory Sample/Preload instruction allows a snapshot of the normal
operation of the component to be taken and examined. It also allows data values to
be loaded into the latched parallel outputs of the Boundary-scan Shift Register prior
to selection of the other boundary-scan test instructions.
Extest
(00000)
Boundary-scan Register
The mandatory Extest instruction allows testing of off-chip circuitry and board level
interconnections. Data would typically be loaded onto the latched parallel outputs of
Boundary-scan Shift Register using the Sample/Preload instruction prior to selection
of the Extest instruction.
Bypass
(11111)
Bypass Register
Places the 1-bit bypass register between the TDI and TDO pins, which allows the
BST data to pass synchronously through the selected device to adjacent devices
during normal device operation. The Bypass instruction can be entered by holding
TDI at a constant high value and completing an Instruction-scan cycle.
Idcode
(00001)
Boundary-scan Register
Selects the Idcode register and places it between TDI and TDO, allowing the Idcode
to be serially shifted out of TDO. The Idcode instruction permits blind interrogation of
the components assembled onto a printed circuit board. Thus, in circumstances
where the component population may vary, it is possible to determine what
components exist in a product.
High-Z
(00101)
Bypass Register
The High-Z instruction places the component in a state which all of its system logic
outputs are placed in an inactive drive state (e.g., high impedance). In this state, an
in-circuit test system may drive signals onto the connections normally driven by a
component output without incurring the risk of damage to the component. The High-Z
instruction also forces the Bypass Register between TDI and TDO
Intest
(00011)
Boundary-scan Register
The Intest instruction selects the boundary scan register preparatory to applying
tests to the logic core of the device. This permits testing of on-chip system logic while
the component is already on the board
Table 4:
JTAG Pin Description
Pin
Name
Description
TCK
Test Clock Input
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins,
respectively.
TMS
Test Mode Select
Serial input pin selects the JTAG instruction mode. TMS should be driven high during
user mode operation.
TDI
Test Data Input
Serial input pin for instructions and test data. Data is shifted in on the rising edge of
TCK.
TDO
Test Data Output
Serial output pin for instructions and test data. Data is shifted out on the falling edge
of TCK. The signal is 3-stated if data is not being shifted out of the device.
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參數(shù)描述 |
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| XCR3128XL-10CS144C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144C IC SYSTEM GATE |
| XCR3128XL-10CS144I | 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144I IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CS144I-STI | 制造商:Xilinx 功能描述: |
| XCR3128XL-10CSG144C | 制造商:Xilinx 功能描述: 制造商:Xilinx 功能描述:XLXXCR3128XL-10CSG144C IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CSG144I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
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