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參數(shù)資料
| 型號(hào)： | XCR3128XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | CoolRunner XPLA3 CPLD(CoolRunner XPLA3復(fù)雜可編程邏輯器件) |
| 中文描述： | 的CoolRunner CPLD的XPLA3（的CoolRunner XPLA3復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 109K |
| 代理商： | XCR3128XL |
R
Timing Model
The XPLA3 architecture follows a timing model that allows
deterministic timing in design and redesign. The basic tim-
ing model is shown in
Figure 7
. There is a fast path (T
LOGI1
)
into the macrocell which is used if there is a single product
term. The T
LOGI2
path is used for multiple product term tim-
ing. For optimization of logic, the XPLA3 CPLD architecture
includes a Fold-back NAND path (T
LOGI3
). There is a fast
input path to each macrocell if used as an Input Register
(T
FIN
). XPLA3 also includes universal control terms (T
UDA
)
that can be used for synchronization of the macrocell regis-
ters in different function blocks. There is slew rate control
and output enable control on a per macrocell basis.
JTAG Testing Capability
JTAG is the commonly used acronym for the Boundary
Scan Test (BST) feature defined for integrated circuits by
IEEE Standard 1149.1. This standard defines input/output
pins, logic control functions, and commands that facilitate
both board and device level testing without the use of spe-
cialized test equipment. XPLA3 devices use the JTAG Inter-
face for In-System Programming/Reprogramming. The
JTAG command set is implemented as described in
Table 3
.
As implemented in XPLA3, the JTAG Port includes four of
the five pins (refer to
Table 4
) described in the JTAG specifi-
cation: TCK, TMS, TDI, and TDO. The fifth signal defined by
the JTAG specification is TRST (Test Reset). TRST is con-
sidered an optional signal, since it is not actually required to
perform BST or ISP. The XPLA3 saves an I/O pin for general
purpose use by not implementing the optional TRST signal
in the JTAG interface. Instead, the XPLA3 supports the test
reset functionality through the use of its power-up reset cir-
cuit.
Port Enable Pin
The Port Enable pin is used to reclaim TMS, TDO, TDI, and
TCK for JTAG ISP programming if the user has defined
these pins as general purpose I/O during device program-
ming. For ease of use, XPLA3 devices are shipped with the
JTAG port pins enabled. Please note that the Port Enable
pin must be low logic level during the power-up sequence
for the device to operate properly.
During device programming, the JTAG ISP pins can be left
as is or reconfigured as user specific I/O pins. If the JTAG
ISP pins have been used for I/O pins, simply applying high
logic level to the Port Enable pin converts the JTAG ISP pins
back to their respective programming function and the
device can be reprogrammed via ISP. After completing the
desired JTAG ISP programming function, simply return Port
Enable to Ground. This will re-establish the JTAG ISP pins
to their respective I/O function. Note that reconfiguring the
JTAG port pins as I/Os makes these pins non-JTAG ISP
functional until reclaimed by port enable. If the JTAG pins
are not required as I/O, port enable should be permanently
tied to GND. Pins associated with the JTAG port have inter-
nal weak pull ups enabled to terminate the pins. However,
in noisy environments, external 10K pull ups are recom-
mended.
The XPLA3 family allows the macrocells associated with
these pins to be used as buried logic when the JTAG/ISP
function is enabled.
Figure 7:
XPLA3 Timing Model
T
IN
T
F
T
OUT
T
EN
T
SLEW
T
LOGI1,2
DLT
Q
CE
S/R
T
LOGI3
T
FIN
T
GCK
T
UDA
DS017_02_042800
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3128XL-10CS144C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144C IC SYSTEM GATE |
| XCR3128XL-10CS144I | 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144I IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CS144I-STI | 制造商:Xilinx 功能描述: |
| XCR3128XL-10CSG144C | 制造商:Xilinx 功能描述: 制造商:Xilinx 功能描述:XLXXCR3128XL-10CSG144C IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CSG144I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
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