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參數(shù)資料
| 型號： | XCR3128XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | CoolRunner XPLA3 CPLD(CoolRunner XPLA3復雜可編程邏輯器件) |
| 中文描述： | 的CoolRunner CPLD的XPLA3（的CoolRunner XPLA3復雜可編程邏輯器件） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 109K |
| 代理商： | XCR3128XL |
DS012 (v1.3) February 9, 2001
Advance Product Specification
1-800-255-77781
2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
Fast Zero Power (FZP) design technique provides
ultra-low power and very high speed
Innovative XPLA3 architecture combines high speed
with extreme flexibility
Based on industry's first TotalCMOS PLD - both
CMOS design and process technologies
Advanced 0.35
μ
five metal layer E
2
CMOS process
-
1,000 erase/program cycles guaranteed
-
20 years data retention guaranteed
3V, In-System Programmable (ISP) using JTAG IEEE
1149.1 interface
-
Full Boundary Scan Test (IEEE 1149.1)
-
Fast programming times
Ultra-low static power of less than 100
μ
A
Support for complex asynchronous clocking
-
16 product term clocks and four local control term
clocks per function block
-
Four global clocks and one universal control term
clock per device
Excellent pin retention during design changes
5V tolerant I/O pins
Input register set up time of 1.7 ns
Single pass logic expandable to 48 product terms
High-speed pin-to-pin delays of 5.0 ns
Slew rate control per output
100% routable
Security bit prevents unauthorized access
Supports hot-plugging capability
Design entry/verification using Xilinx or industry
standard CAE tools
Innovative Control Term structure provides:
-
Asynchronous macrocell clocking
-
Asynchronous macrocell register preset/reset
-
Clock enable control per macrocell
Four output enable controls per function block
Foldback NAND for synthesis optimization
Global 3-state which facilitates "bed of nails" testing
Available in Chip-scale BGA, PLCC, and QFP
packages
Commercial grade and extended voltage industrial
grade available
0
CoolRunner
XPLA3 CPLD
DS012 (v1.3) February 9, 2001
0
14
Advance Product Specification
R
Table 1:
CoolRunner XPLA3 Device Family
XCR3032XL
32
800
32
5
1.7
3.5
175
XCR3064XL
64
1600
64
6
2
4
145
XCR3128XL
128
3200
128
6
2
4
145
XCR3256XL
256
6400
256
7.5
2
4.5
140
XCR3384XL
384
9600
384
7.5
2
4.5
127
Macrocells
Usable Gates
Registers
T
PD
(ns)
T
SU
(ns)
T
CO
(ns)
Fsystem (MHz)
Table 2:
CoolRunner XPLA3 Packages and User I/O Pins
XCR3032XL
36
36
36
-
-
-
-
-
-
-
XCR3064XL
36
36
40
48
68
-
-
-
-
-
XCR3128XL
-
-
-
-
84
108
108
-
-
-
XCR3256XL
-
-
-
-
-
-
120
164
164
164
XCR3384XL
-
-
-
-
-
-
-
172
212
-
44-pin PLCC
44-pin 1mm VQFP
48-pin 0.8mm CSP
56-pin 0.5mm CSP
100-pin 1mm VQFP
144-pin 0.8mm CSP
144-pin 1.4mm VQFP
208-pin PQFP
256-pin 1.0mm BGA
280-pin 0.8mm CSP
相關PDF資料 |
PDF描述 |
|---|---|
| XCR3256XL-12TQ144I | Connector |
| XCR3256XL-7CS280C | 256 Macrocell CPLD |
| XCR3256XL-7CS280I | Connector |
| XCR3256XL-7FT256C | 256 Macrocell CPLD |
| XCR3256XL-7FT256I | 256 Macrocell CPLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3128XL-10CS144C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144C IC SYSTEM GATE |
| XCR3128XL-10CS144I | 制造商:Xilinx 功能描述:XLXXCR3128XL-10CS144I IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CS144I-STI | 制造商:Xilinx 功能描述: |
| XCR3128XL-10CSG144C | 制造商:Xilinx 功能描述: 制造商:Xilinx 功能描述:XLXXCR3128XL-10CSG144C IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3128XL-10CSG144I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 3K GATES 128 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
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