參數(shù)資料
型號(hào): XC7445B
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: RISC Microprocessor Hardware Specifications
中文描述: RISC微處理器硬件規(guī)格
文件頁數(shù): 27/64頁
文件大小: 1127K
代理商: XC7445B
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
27
Electrical and Thermal Characteristics
Table 13
provides the L3 bus interface AC timing specifications for the configuration shown in
Figure 11
, assuming
the timing relationships of
Figure 12
and the loading of
Figure 8
.
Table 13. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See
Table 4
.
Parameter
Symbol
All Speed Grades
6
Unit Notes
L3OH0 = 0, L3OH1 = 0 L3OH0 = 0, L3OH1 =1 L3OH0 = 1, L3OH1 = 0 L3OH0 = 1, L3OH1 = 1
Min
Max
Min
Max
Min
Max
Min
Max
L3_CLK rise
and fall time
t
L3CR
,
t
L3CF
1.0
1.0
1.0
1.0
ns
1, 5
Setup times:
Data and
parity
t
L3DVEH
1.5
1.5
1.5
1.5
ns
2, 5
Input hold
times: Data
and parity
t
L3DXEH
0.5
0.5
0.5
0.5
ns
2, 5
Valid times:
Data and
parity
t
L3CHDV
t
L3_CLK
/4
+ 1.00
t
L3_CLK
/4
+ 0.80
t
L3_CLK
/4
+ 0.60
t
L3_CLK
/4
+ 0.40
ns
3, 4, 5
Valid times: All
other outputs
t
L3CHOV
t
L3_CLK
/4
+ 1.00
t
L3_CLK
/4
+ 0.80
t
L3_CLK
/4
+ 0.60
t
L3_CLK
/4
+ 0.40
ns
4
Output hold
times: Data
and parity
t
L3CHDX
t
L3_CLK
/4
– 0.40
t
L3_CLK
/4
– 0.60
t
L3_CLK
/4
– 0.80
t
L3_CLK
/4
– 1.00
ns
3, 4, 5
Output hold
times: All other
outputs
t
L3CHOX
t
L3_CLK
/4
– 0.40
t
L3_CLK
/4
– 0.60
t
L3_CLK
/4
– 0.80
t
L3_CLK
/4
– 1.00
ns
4, 5
L3_CLK to
high
impedance:
Data and
parity
t
L3CHDZ
2.0
2.0
2.0
2.0
ns
5
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