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參數(shù)資料
| 型號(hào)： | XC7445B |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 11/64頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | XC7445B |
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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
11
Electrical and Thermal Characteristics
Figure 2
shows the undershoot and overshoot voltage on the MPC7455.
Figure 2. Overshoot/Undershoot Voltage
The MPC7455 provides several I/O voltages to support both compatibility with existing systems and migration to
future systems. The MPC7455 core voltage must always be provided at nominal 1.3 V (see
Table 4
for actual
recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are provided through separate sets
of supply pins and may be provided at the voltages shown in
Table 3
. The input voltage threshold for each bus is
selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage
will swing from GND to the maximum voltage applied to the OV
DD
or GV
DD
power pins.
Table 3. Input Threshold Voltage Setting
BVSEL Signal
Processor Bus Input
Threshold is Relative to:
L3VSEL Signal
5
L3 Bus Input Threshold is
Relative to:
Notes
0
1.8 V
0
1.8 V
1, 4
HRESET
Not Available
HRESET
1.5 V
1, 3
HRESET
2.5 V
HRESET
2.5 V
1, 2
1
2.5 V
1
2.5 V
1
Notes:
1.
Caution:
The input threshold selection must agree with the OV
DD
/GV
DD
voltages supplied. See notes in
Table 2
.
2. To select the 2.5-V threshold option for the processor bus, BVSEL should be tied to HRESET so that the two signals
change state together. Similarly, to select 2.5 V for the L3 bus, tie L3VSEL to HRESET. This is the preferred method
for selecting this mode of operation.
3. Applicable to L3 bus interface only. HRESET is the inverse of HRESET.
4. If used, pulldown resistors should be less than 250
.
5. Not implemented on MPC7445.
V
IH
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
of t
SYSCLK
OV
DD
/GV
DD
+ 20%
OV
DD
/GV
DD
+ 5%
V
IL
OV
DD
/GV
DD
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