參數(shù)資料
型號(hào): XC7445B
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: RISC Microprocessor Hardware Specifications
中文描述: RISC微處理器硬件規(guī)格
文件頁數(shù): 25/64頁
文件大?。?/td> 1127K
代理商: XC7445B
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
25
Electrical and Thermal Characteristics
Figure 9
shows the typical connection diagram for the MPC7455 interfaced to MSUG2 SRAMs such as the
Freescale MCM64E836.
Figure 9. Typical Source Synchronous 2-Mbyte L3 Cache DDR Interface
Aligned Signals
{L3DATA[0:15],
{L3DATA[16:31],
{L3_DATA[32:47],
L3ADDR[17:0]
L3_CNTL[0]
L3_CLK[0]
L3_CLK[1]
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3ECHO_CLK[2]
L3_ECHO_CLK[3]
{L3DATA[48:63],
L3DP[0:1]}
L3DP[2:3]}
L3DP[4:5]}
L3DP[6:7]}
CQ
SA[17:0]
B1
CK
B2
SRAM 0
SRAM 1
SA[17:0]
B1
B2
CQ
D[0:17]
D[18:35]
CQ
CK
CQ
D[0:17]
D[18:35]
L3_CNTL[1]
NC
NC
GND
GND
GND
NC
NC
GND
GND
GND
MPC7455
Denotes
Receive (SRAM
to MPC7455)
Denotes
Transmit
(MPC7455 to
SRAM)
Aligned Signals
GV
DD
/2
1
GV
DD
/2
1
CQ
CK
B3
G
CQ
LBO
CQ
CK
B3
G
CQ
LBO
Note:
1. Or as recommended by SRAM manufacturer for single-ended clocking.
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