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參數(shù)資料
| 型號： | XC7445B |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 10/64頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | XC7445B |
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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
10
Freescale Semiconductor
Electrical and Thermal Characteristics
5
Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7455.
5.1 DC Electrical Characteristics
The tables in this section describe the MPC7455 DC electrical characteristics.
Table 2
provides the absolute
maximum ratings.
Table 2. Absolute Maximum Ratings
1
Characteristic
Symbol
Maximum Value
Unit
Notes
Core supply voltage
V
DD
–0.3 to 1.95
V
4
PLL supply voltage
AV
DD
–0.3 to 1.95
V
4
Processor bus supply voltage
BVSEL = 0
OV
DD
–0.3 to 1.95
V
3, 6
BVSEL = HRESET or OV
DD
OV
DD
–0.3 to 2.7
V
3, 7
L3 bus supply voltage
L3VSEL = HRESET
GV
DD
–0.3 to 1.65
V
3, 8
L3VSEL = 0
GV
DD
–0.3 to 1.95
V
3, 9
L3VSEL = HRESET or GV
DD
GV
DD
–0.3 to 2.7
V
3, 10
Input voltage
Processor bus
V
in
–0.3 to OV
DD
+ 0.3
V
2, 5
L3 bus
V
in
–0.3 to GV
DD
+ 0.3
V
2, 5
JTAG signals
V
in
–0.3 to OV
DD
+ 0.3
V
Input voltage
Processor bus
V
in
–0.3 to OV
DD
+ 0.3
V
2, 5
JTAG signals
V
in
–0.3 to OV
DD
+ 0.3
V
Storage temperature range
T
stg
–55 to 150
°C
Notes
:
1. Functional and tested operating conditions are given in
Table 4
. Absolute maximum ratings are stress ratings only,
and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
2.
Caution
: Vin must not exceed OV
DD
or GV
DD
by more than 0.3 V at any time including during power-on reset.
3.
Caution
: OV
DD
/GV
DD
must not exceed V
DD
/AV
DD
by more than 2.0 V during normal operation; this limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
4.
Caution
: V
DD
/AV
DD
must not exceed OV
DD
/GV
DD
by more than 1.0 V during normal operation; this limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
5. V
in
may overshoot/undershoot to a voltage and for a maximum duration as shown in
Figure 2
.
6. BVSEL must be set to 0, such that the bus is in 1.8 V mode.
7. BVSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode.
8. L3VSEL must be set to HRESET (inverse of HRESET), such that the bus is in 1.5 V mode.
9. L3VSEL must be set to 0, such that the bus is in 1.8 V mode.
10.L3VSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode.
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