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參數(shù)資料
| 型號(hào)： | XC5000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 7/48頁 |
| 文件大?。?/td> | 434K |
| 代理商： | XC5000 |
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3
The TLM process allows significant improvements in the
routing structure. Each XC5200 VersaBlock element
has complete intra-CLB routing, the LIM, and offers four
direct routing connections to each of the four
neighboring CLBs (North, South, East, and West). Any
function generator or flip-flop thus has unrestricted
connectivity to 19 other function generators or flip-
flops: three in its own CLB, and 16 in the adjacent
CLBs. These direct connects do not compete with the
general routing resources (see Table 3).
Each XC5200 3-state buffer (TBUF) can drive up to two
horizontal Longlines; each XC4000 TBUF accesses
only one horizontal Longline.
There is a special racetrack, the VersaRing, between
the outer edge of the core CLB array and the ring of
IOBs, providing significant help in overcoming the
problems caused by early locking of I/O pins.
There are no internal pull-ups for XC5200 Longlines.
Figure 1.
XC5200 Architectural Overview
Table 3.
Routing Resource Comparison
Resource
XC5200
XC4000
Single-length Lines
10
8
Double-length Lines
4
4
Longlines
8
6
Direct Connects
8
0
VersaRing
yes
no
X4955
GRM
Input/Output Blocks (IOBs)
Block
GRM
Block
VersaRing
VersaRing
GRM
Block
GRM
Block
GRM
Block
GRM
Block
GRM
Block
GRM
Block
GRM
Block
V
V
Architectural Overview
Figure 1 presents a simplified, conceptual overview of the
XC5200 architecture. Similar to conventional FPGAs, the
XC5200
family
consists
programmable
logic
blocks,
interconnect. Unlike other FPGAs, however, the logic and
local routing resources of the XC5200 family are
combined in flexible VersaBlocks. General-purpose
routing connects to the VersaBlock through the General
Routing Matrix (GRM).
of
programmable
and
IOBs,
programmable
VersaBlock: Abundant Local Routing Plus Versatile
Logic
The basic logic element in each VersaBlock structure is
the Logic Cell, shown in Figure 2. Each LC contains a 4-
input function generator (F), a storage device (FD), and
control logic. There are five independent inputs and three
outputs to each LC. The independence of the inputs and
outputs allows the software to maximize the resource
utilization within each LC. Each Logic Cell also contains a
direct feedthrough path that does not sacrifice the use of
either the function generator or the register; this feature is
a first for FPGAs. The storage device is configurable as
either a D flip-flop or a latch. The control logic consists of
carry logic for fast implementation of arithmetic functions,
which can also be configured as a cascade chain allowing
decode of very wide input functions.
The XC5200 CLB consists of four LCs, as shown in
Figure 3. Each CLB has 20 independent inputs and 12
independent outputs. The top and bottom pairs of LCs can
be configured to implement 5-input functions. The
challenge of FPGA implementation software has always
been to maximize the usage of logic resources. The
XC5200 family addresses this issue by surrounding each
CLB with two types of local interconnect — the LIM and
direct connects. These two interconnect resources,
combined with the CLB, form the VersaBlock, represented
in Figure 4.
Figure 2.
XC5200 Logic Cell (Four LCs per CLB)
X4956
F4
F3
F
FD
F2
F1
D
Q
X
DO
DI
CO
CI
CE CK
CLR
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