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參數(shù)資料
| 型號： | XC5000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 5/48頁 |
| 文件大小： | 434K |
| 代理商： | XC5000 |
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XC5200
Logic Cell Array Family
Preliminary (v1.0)
Product Description
Table 1.
Initial XC5200 Field-Programmable Gate Array Family Members
Device
XC5202
XC5204
XC5206
XC5210
XC5215
Typical Gate Range
2,200 -
2,700
3,900 -
4,800
6,000 -
7,500
10,000 -
12,000
14,000 -
18,000
VersaBlock Array
8 x 8
10 x 12
14 x 14
18 x 18
22 x 22
Number of CLBs
64
120
196
324
484
Number of Flip-Flops
256
480
784
1,296
1,936
Number of I/Os
84
124
148
196
244
TBUFs per Horizontal Longline
10
14
16
20
24
Fully supported by XACT
Development System
— Includes complete support for XACT-Performance,
X-BLOX, Unified Libraries, Relationally Placed
Macros (RPMs), XDelay, and XChecker
— Wide selection of PC and workstation platforms
— Interfaces to more than 100 third-party CAE tools
Description
The XC5200 Field-Programmable Gate Array Family is
engineered to deliver the lowest cost of any FPGA family.
By optimizing the new XC5200 architecture for TLM
technology and 0.6-
μ
m CMOS SRAM process, dramatic
advances have been made in silicon efficiency. These
advances position the XC5200 family as a cost-effective,
high-volume alternative to gate arrays.
Building on experiences gained with three previous
successful SRAM FPGA families, the XC5200 family
brings a robust feature set to high-density programmable
logic design. The VersaBlock logic module, the VersaRing
I/O interface, and a rich hierarchy of interconnect
resources combine to enhance design flexibility and
reduce time-to-market.
Complete support for the XC5200 family is delivered
through the familiar XACT software environment. The
XC5200 family is fully supported on popular workstation
and PC platforms. Popular design entry methods are fully
supported, including ABEL, schematic capture, and
synthesis. Designers utilizing logic synthesis can use their
existing Synopsys, Viewlogic, Mentor, and Exemplar tools
to design with the XC5200 devices.
Features
High-density family of Field-Programmable Gate Arrays
(FPGAs)
Design- and process-optimized for low cost
— 0.6-
μ
m three-layer metal (TLM) process
System performance up to 50 MHz
SRAM-based, in-system reprogrammable architecture
Flexible architecture with abundant routing resources
— VersaBlock logic module
— VersaRing I/O interface
— Dedicated cell-feedthrough path
— Hierarchical interconnect structure
— Extensive registers/latches
— Dedicated carry logic for arithmetic functions
— Cascade chain for wide input functions
— Dedicated IEEE 1149.1 boundary-scan logic
— Internal 3-state bussing capability
— Four global low-skew clock or signal distribution nets
— Globally selectable CMOS or TTL input thresholds
— Output slew-rate control
— 8-mA sink current per output
Configured by loading binary file
— Unlimited reprogrammability
— Six programming modes, including high-speed
Express mode
100% factory tested
100% footprint compatibility for common packages
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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