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參數(shù)資料
| 型號： | XC5000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 12/48頁 |
| 文件大小： | 434K |
| 代理商： | XC5000 |
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XC5200 Logic Cell Array Family
Preliminary (v1.0)
8
Figure 5.
Two LUTs in Parallel Combined to Create a 5-input Function
out
Q
Qout
DO
Q
D
FD
X
FD
CO
DI
X
CLR
LC0
CK
CE
5-Input Function
D
DO
F5_MUX
DI
F
F4
F3
F2
F1
F4
F3
F2
F1
I1
I2
I3
I4
I5
CI
F
LC1
X5710
Detailed Functional Description
CLB Logic
Figure 3 shows the logic in the XC5200 CLB, which
consists of four Logic Cells (LC[3:0]). Each Logic Cell
consists of an independent 4-input Lookup Table (LUT),
and a D-Type flip-flop or latch with common clock, clock
enable, and clear, but individually selectable clock polarity.
Additional logic features provided in the CLB are:
High-speed carry propagate logic.
High-speed pattern decoding.
High-speed direct connection to flip-flop D-inputs.
Each flip-flop can be programmed individually as either
a transparent, level-sensitive latch or a D flip-flop.
Four 3-state buffers with a shared Output Enable.
Two 4-input LUTs can be combined to form an
independent 5-input LUT.
5-Input Functions
Figure 5 illustrates how the outputs from the LUTs from
LC0 and LC1 can be combined with a 2:1 multiplexer
(F5_MUX) to provide a 5-input function. The outputs from
the LUTs of LC2 and LC3 can be similarly combined.
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