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參數(shù)資料
| 型號： | XC5000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 8/48頁 |
| 文件大?。?/td> | 434K |
| 代理商： | XC5000 |
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XC5200 Logic Cell Array Family
Preliminary (v1.0)
4
Figure 3.
Configurable Logic Block
X4957
F4
F3
F
FD
LC3
LC2
LC1
LC0
F2
F1
D
Q
X
DO
DI
CO
F4
F3
F
FD
F2
F1
D
Q
X
DO
DI
F4
F3
F
FD
F2
F1
D
Q
X
DO
DI
F4
F3
F
FD
F2
F1
D
Q
X
DO
DI
CI
CE CK
CLR
Figure 4.
VersaBlock
The LIM provides 100% connectivity of the inputs and
outputs of each LC in a given CLB. The benefit of the LIM
is that no general routing resources are required to
connect feedback paths within a CLB. The LIM connects
to the GRM via 24 bidirectional nodes.
The direct connects allow immediate connections to
neighboring CLBs, once again without using any of the
general interconnect. These two layers of local routing
resource improve the granularity of the architecture,
effectively making the XC5200 family a “sea of logic cells.”
Each VersaBlock has four 3-state buffers that share a
common enable line and directly drive horizontal
Longlines, creating robust on-chip bussing capability. The
VersaBlock allows fast, local implementation of logic
functions, effectively implementing user designs in a
hierarchical fashion. These resources also minimize local
routing congestion and improve the efficiency of the
general interconnect, which is used for connecting larger
groups of logic. It is this combination of both fine-grain and
coarse-grain architecture attributes that maximize logic
utilization in the XC5200 family. This symmetrical structure
takes full advantage of the third metal layer, freeing the
placement software to pack user logic optimally with
minimal routing restrictions.
X5707
CLB
LC3
Direct Connects
TS
GRM
LIM
4
4
4
4
4
LC2
LC1
LC0
4
4
4
4
24
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