參數(shù)資料
型號(hào)： XC5000
廠商： Xilinx, Inc.
英文描述： Logic Cell Array Family
中文描述： 邏輯單元陣列系列
文件頁(yè)數(shù)： 16/48頁(yè)
文件大?。?/td> 434K
代理商： XC5000
XC5200 Logic Cell Array Family
Preliminary (v1.0)
12
VersaBlock Routing
Local Interconnect Matrix
The GRM connects to the VersaBlock via 24 bidirectional
ports (M0-M23). Excluding direct connections, global nets,
and 3-statable Longlines, all VersaBlock inputs and
outputs connect to the GRM via these 24 ports. Four 3-
statable unidirectional signals (TQ0-TQ3) drive out of the
VersaBlock directly onto the horizontal Longlines. Two
horizontal global nets (GH0 and GH1) and two vertical
global nets (GV0 and GV1) connect directly to every CLB
clock pin; they can connect to other CLB inputs via the
GRM. Each CLB also has four unidirectional direct
connects to each of its four neighboring CLBs. These
direct connects can also feed directly back to the CLB
(see Figure 10).
In addition, each CLB has 16 direct inputs, four direct
connections from each of the neighboring CLBs. These
direct connections provide high-speed local routing that
bypasses the GRM.
The 13 CLB outputs (12 LC outputs plus a V
cc
/GND
signal) connect to the eight VersaBlock outputs via the
output multiplexers, which consist of eight fully populated
13-to-1 multiplexers. Of the eight VersaBlock outputs, four
signals drive each neighboring CLB directly, and provide a
direct feedback path to the input multiplexers. The four
remaining multiplexer outputs can drive the GRM through
four TBUFs (TQ0-TQ3). All eight multiplexer outputs can
connect to the GRM through the bidirectional M0-M23
signals. All eight signals also connect to the input
multiplexers and are potential inputs to that CLB.
CLB inputs have several possible sources: the 24 signals
from the GRM, 16 direct connections from neighboring
VersaBlocks, four signals from global, low-skew buffers
(GH0, GH1, GV0, and GV1), and the four signals from the
CLB output multiplexers. Unlike the output multiplexers,
the input multiplexers are not fully populated; i.e., only a
subset of the available signals can be connected to a
given CLB input. The flexibility of LUT input swapping and
LUT mapping compensates for this limitation. For
example, if a 2-input NAND gate is required, it can be
mapped into any of the four LUTs, and use any two of the
four inputs to the LUT.
Direct Connects
The unidirectional direct-connect segments are connected
to the logic input/output pins through the CLB’s input and
output
multiplexer
array,
programmable routing matrix altogether. These lines are
intended to increase the routing channel utilization where
possible, while simultaneously reducing the delay incurred
in speed-critical connections.
and
thus
bypass
the
The direct connects also provide a high-speed path from
the edge CLBs to the VersaRing input/output buffers, and
thus reduce set-up time, clock-to-out, and combinational
propagation delay.
The direct connects are ideal for developing customized
RPM cells. Using direct connects improves the macro
performance, and leaves the other routing channels intact
for improved routing. Direct connects can also route
through a CLB using one of the four cell-feedthrough
paths.
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