參數(shù)資料
型號(hào)： XC5000
廠商： Xilinx, Inc.
英文描述： Logic Cell Array Family
中文描述： 邏輯單元陣列系列
文件頁數(shù)： 14/48頁
文件大小： 434K
代理商： XC5000
XC5200 Logic Cell Array Family
Preliminary (v1.0)
10
Figure 7.
XC5200 CY_MUX Used for Decoder Cascade Logic
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
AND
AND
F=0
DI
DI
DI
DI
FD
FD
FD
cascade out
out
DO
D
X
LC3
DO
DO
DO
D
Q
LC2
X
CI
cascade in
CY_MUX
CY_MUX
CY_MUX
CY_MUX
CY_MUX
FD
X
LC1
Initialization of
carry chain (One Logic Cell)
LC0
CK
CE
CLR
D
D
Q
Q
X
Q
CO
AND
AND
X5708
Cascade Function
Each CY_MUX can be connected to the CY_MUX in the
adjacent LC to provide cascadable decode logic. Figure 7
illustrates how the 4-input function generators can be
configured to take advantage of these four cascaded
CY_MUXes. Note that AND and OR cascading are
specific cases of a general decode. In AND cascading all
bits are decoded equal to logic one, while in OR
cascading all bits are decoded equal to logic zero. The
flexibility of the LUT achieves this result.
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