參數(shù)資料
型號(hào)： XC5000
廠商： Xilinx, Inc.
英文描述： Logic Cell Array Family
中文描述： 邏輯單元陣列系列
文件頁(yè)數(shù)： 21/48頁(yè)
文件大?。?/td> 434K
代理商： XC5000
R
17
Table 5.
Configuration Modes
Mode
M2
M1
M0
CCLK
Data
Master Serial
0
0
0
output
Bit-Serial
Slave Serial
1
1
1
input
Bit-Serial
Master Parallel up
1
0
0
output
Byte-Wide, 00000
↑
Master Parallel down
1
1
0
output
Byte-Wide, 3FFFF
↓
Peripheral Synchronous *
0
1
1
input
Byte-Wide
Peripheral Asynchronous
1
0
1
output
Byte-Wide
Express
0
1
0
input
Byte-Wide
Reserved
0
0
1
—
—
* Peripheral Synchronous can be considered byte-wide Slave Parallel
Configuration
Configuration is the process of loading design-specific
programming data into one or more LCA devices to define
the functional operation of the internal blocks and their
interconnections. This is somewhat like loading the
command registers of a programmable peripheral chip.
Each configuration bit defines the state of a static memory
cell that controls either a function LUT bit, a multiplexer
input, or an interconnect pass transistor. The XACT
development system translates the design into a netlist
file. It automatically partitions, places, and routes the logic
and generates the configuration data in PROM format.
Modes
The XC5200 family has seven modes of configuration,
selected by a 3-bit input code applied to the LCA mode
pins (M0, M1, and M2). There are three self-clocking
Master modes, two Peripheral modes, a Slave serial
mode, and a new high-speed Slave parallel mode called
the Express. See Table 5.
Brief descriptions of the seven modes are provided below.
For details on all modes except Express, see pages 2-32
through 2-41 of the 1994 Xilinx Programmable Logic Data
Book.
Master Modes
The Master modes use an internal oscillator to generate
CCLK for driving potential slave devices, and to generate
address and timing for external PROM(s) containing the
configuration data. Master Parallel (up or down) modes
generate the CCLK signal and PROM addresses, and
receive byte parallel data, which is internally serialized
into the LCA data-frame format. The up and down
selection generates starting addresses at either zero or
3FFFF, to be compatible with different microprocessor
addressing conventions. The Master Serial Mode
generates CCLK and receives the configuration data in
serial form from configuration data in serial form from a
Xilinx serial-configuration PROM.
Peripheral Modes
The two Peripheral modes accept byte-wide data from a
bus. A READY/BUSY status is available as a handshake
signal. In the asynchronous mode, the internal oscillator
generates a CCLK burst signal that serializes the byte-
wide data. In the synchronous mode, an externally
supplied clock input to CCLK serializes the data.
Slave Serial Mode
In the Slave Serial mode, the LCA device receives serial-
configuration data on the rising edge of CCLK and, after
loading its configuration, passes additional data out,
resynchronized on the next falling edge of CCLK. Multiple
slave devices with identical configurations can be wired
with parallel DIN inputs so that the devices can be
configured simultaneously.
Daisy Chaining
Multiple devices may be daisy-chained together so that
they may be programmed using a single bitstream. The
first device in the chain may be set to operate in any
mode. All devices except the first device in the chain must
be set to operate in Slave Serial mode.
All CCLK pins are tied together and the data chain passes
from DOUT to DIN of successive devices along the chain.
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