參數(shù)資料
型號(hào)： XC3S1200E-4FGG400I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 215/227頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3E 1200K 400FBGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-3E
LAB/CLB數(shù)： 2168
邏輯元件/單元數(shù)： 19512
RAM 位總計(jì)： 516096
輸入/輸出數(shù)： 304
門數(shù)： 1200000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 400-BGA
供應(yīng)商設(shè)備封裝： 400-FBGA（21x21）
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
88
Voltage Compatibility
The FPGA’s parallel Flash interface signals are within
I/O Banks 1 and 2. The majority of parallel Flash PROMs
use a single 3.3V supply voltage.
Consequently, in most
cases, the FPGA’s VCCO_1 and VCCO_2 supply voltages
must also be 3.3V to match the parallel Flash PROM. There
are some 1.8V parallel Flash PROMs available and the
FPGA interfaces with these devices if the VCCO_1 and
VCCO_2 supplies are also 1.8V.
Power-On Precautions if PROM Supply is Last in
Sequence
Like SPI Flash PROMs, parallel Flash PROMs typically
require some amount of internal initialization time when the
supply voltage reaches its minimum value.
The PROM supply voltage also connects to the FPGA’s
VCCO_2 supply input. In many systems, the PROM supply
feeding the FPGA’s VCCO_2 input is valid before the
FPGA’s other VCCINT and VCCAUX supplies, and
consequently, there is no issue. However, if the PROM
supply is last in the sequence, a potential race occurs
between the FPGA and the parallel Flash PROM. See
for a similar description of the issue for SPI Flash PROMs.
Supported Parallel NOR Flash PROM Densities
Table 60 indicates the smallest usable parallel Flash PROM
to program a single Spartan-3E FPGA. Parallel Flash
density is specified in bits but addressed as bytes. The
FPGA presents up to 24 address lines during configuration
but not all are required for single FPGA applications.
Table 60 shows the minimum required number of address
lines between the FPGA and parallel Flash PROM. The
actual number of address line required depends on the
density of the attached parallel Flash PROM.
A multiple-FPGA daisy-chained application requires a
parallel Flash PROM large enough to contain the sum of the
FPGA file sizes. An application can also use a larger-density
parallel Flash PROM to hold additional data beyond just
FPGA configuration data. For example, the parallel Flash
PROM can also contain the application code for a MicroBlaze
RISC processor core implemented within the Spartan-3E
FPGA. After configuration, the MicroBlaze processor can
execute directly from external Flash or can copy the code to
other, faster system memory before executing the code.
DONE
Open-drain
bidirectional I/O
FPGA Configuration Done. Low
during configuration. Goes High
when FPGA successfully completes
configuration. Requires external
330
Ω pull-up resistor to 2.5V.
Low indicates that the FPGA is not
yet configured.
Pulled High via external
pull-up. When High,
indicates that the FPGA is
successfully configured.
PROG_B
Input
Program FPGA. Active Low. When
asserted Low for 500 ns or longer,
forces the FPGA to restart its
configuration process by clearing
configuration memory and resetting
the DONE and INIT_B pins once
PROG_B returns High.
Recommend external 4.7 k
Ω
pull-up resistor to 2.5V. Internal
pull-up value may be weaker (see
Table 78). If driving externally with a
3.3V output, use an open-drain or
open-collector driver or use a
current limiting series resistor.
Must be High to allow configuration
to start.
Drive PROG_B Low and
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
programming access to
Flash PROM pins.
Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Cont’d)
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
V
Table 60: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM
Spartan-3E FPGA
Uncompressed
File Sizes (bits)
Smallest Usable
Parallel Flash PROM
Minimum Required
Address Lines
XC3S100E
581,344
1Mbit
A[16:0]
XC3S250E
1,353,728
2Mbit
A[17:0]
XC3S500E
2,270,208
4Mbit
A[18:0]
XC3S1200E
3,841,184
4Mbit
A[18:0]
XC3S1600E
5,969,696
8Mbit
A[19:0]
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參數(shù)描述
XC3S1200E-4FGG484C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family
XC3S1200E-4FGG484I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family
XC3S1200E-4FT256C 制造商:Xilinx 功能描述:FPGA SPARTAN-3E 1.2M GATES 19512 CELLS 572MHZ 90NM 1.2V 256F - Trays
XC3S1200E-4FT256CES 制造商:Xilinx 功能描述:
XC3S1200E-4FT256I 功能描述:IC FPGA SPARTAN 3E 256FTBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
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