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參數(shù)資料
| 型號(hào)： | XC3S1000-4CPG132C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | FPGA, 192 CLBS, 50000 GATES, PBGA132 |
| 封裝： | LEAD FREE, CSP-132 |
| 文件頁(yè)數(shù)： | 92/198頁(yè) |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000-4CPG132C |
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Spartan-3 FPGA Family: Pinout Descriptions
6
www.xilinx.com
DS099-4 (v1.6) January 17, 2005
Product Specification
R
Detailed, Functional Pin Descriptions
I/O Type: Unrestricted, General-purpose I/O
Pins
After configuration, I/O-type pins are inputs, outputs, bidi-
rectional I/O, three-state outputs, open-drain outputs, or
open-source outputs, as defined in the application
Pins labeled "IO" support all SelectIO signal standards
except differential standards. A given device at most only
has a few of these pins.
A majority of the general-purpose I/O pins are labeled in the
format “IO_Lxxy_#”. These pins support all SelectIO signal
standards, including the differential standards such as
LVDS, ULVDS, BLVDS, RSDS, or LDT.
For additional information, see the "
IOBs
" section in Module
2:
Functional Description
.
Differential Pair Labeling
A pin supports differential standards if the pin is labeled in
the format “Lxxy_#”. The pin name suffix has the following
significance.
Figure 1
provides a specific example showing
a differential input to and a differential output from Bank 2.
‘L indicates differential capability.
"xx" is a two-digit integer, unique for each bank, that
identifies a differential pin-pair.
‘y’ is replaced by ‘P’ for the true signal or ‘N’ for the
inverted. These two pins form one differential pin-pair.
‘#’ is an integer, 0 through 7, indicating the associated
I/O bank.
If unused, these pins are in a high impedance state. The Bit-
stream generator option UnusedPin enables a weak pull-up
or pull-down resistor on all unused I/O pins.
Behavior from Power-On through End of Configu-
ration
During the configuration process, all pins that are not
actively involved in the configuration process are in a
high-impedance state. The HSWAP_EN input determines
whether or not weak pull-up resistors are enabled during
configuration. HSWAP_EN = 0 enables the weak pull-up
resistors. HSWAP_EN = 1 disables the pull-up resistors
allowing the pins to float, which is the desired state for
hot-swap applications.
GND:
Ground supply pins
GND
Supply
Ground:
Ground pins, which are connected to the power supply’s return
path. All pins must be connected.
N.C.:
Unconnected package pins
N.C.
Unconnected Package Pin:
These package pins are unconnected.
Notes:
1.
All unused inputs and bidirectional pins must be tied either High or Low. For unused enable inputs, apply the level that disables the
associated function. One common approach is to activate internal pull-up or pull-down resistors. An alternative approach is to
externally connect the pin to either VCCO or GND.
All outputs are of the totem-pole type — i.e., they can drive High as well as Low logic levels — except for the cases where “Open
Drain” is indicated. The latter can only drive a Low logic level and require a pull-up resistor to produce a High logic level.
2.
Table 2:
Spartan-3 Pin Definitions
(Continued)
Pin Name
Direction
Description
Figure 1:
Differential Pair Labelling
IO_L38P_2
IO_L38N_2
IO_L39P_2
IO_L39N_2
Bank 0
Bank 1
Bank 4
Bank 5
B
B
B
B
Pair Number
Bank Number
Positive Polarity,
True Driver
Negative Polarity,
Inverted Driver
DS099-4_01_042303
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PDF描述 |
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| XC3S1000-4CPG132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQ208C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQ208I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQG208C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQG208I | Spartan-3 FPGA Family: Complete Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4CPG132I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4FG1156C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family : Complete Data Sheet |
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| XC3S1000-4FG320C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 1M GATES 17280 CELLS 630MHZ 1.2V 320FBGA - Trays |
| XC3S1000-4FG320I | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 1M GATES 17280 CELLS 630MHZ 1.2V 320FBGA - Trays |
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