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參數(shù)資料
| 型號(hào)： | XC3S1000-4CPG132C |
| 廠商： | XILINX INC |
| 元件分類(lèi)： | FPGA |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | FPGA, 192 CLBS, 50000 GATES, PBGA132 |
| 封裝： | LEAD FREE, CSP-132 |
| 文件頁(yè)數(shù)： | 100/198頁(yè) |
| 文件大小： | 1605K |
| 代理商： | XC3S1000-4CPG132C |
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Spartan-3 FPGA Family: Pinout Descriptions
14
www.xilinx.com
DS099-4 (v1.6) January 17, 2005
Product Specification
R
described in
Table 9
. The JTAG port is used for bound-
ary-scan testing, device configuration, application debug-
ging, and possibly an additional serial port for the
application. These pins are dedicated and are not available
as user-I/O pins. Every package has four dedicated JTAG
pins and these pins are powered by the +2.5V VCCAUX
supply.
Using JTAG Port After Configuration
The JTAG port is always active and available before, during,
and after FPGA configuration. Add the BSCAN_SPARTAN3
primitive to the design to create user-defined JTAG instruc-
tions and JTAG chains to communicate with internal logic.
Furthermore, the contents of the User ID register within the
JTAG port can be specified as a Bitstream Generation
option. By default, the 32-bit User ID register contains
0xFFFFFFFF.
Precautions When Using the JTAG Port in 3.3V
Environments
The JTAG port is powered by the +2.5V VCCAUX power
supply. When connecting to a 3.3V interface, the JTAG input
pins must be current-limited to 10 mA or less using a series
resistor. Similarly, the TDO pin is a CMOS output powered
from +2.5V. The TDO output can directly drive a 3.3V input
but with reduced noise immunity. See the
3.3V-Tolerant
Configuration Interface
section in Module 2:
Functional
Description
for additional details.
The following interface precautions are recommended when
connecting the JTAG port to a 3.3V interface.
1.
Set any inactive JTAG signals, including TCK, Low
when not actively used.
2.
Limit the drive current into a JTAG input to no more than
10 mA.
VREF: User I/O or Input Buffer Reference
Voltage for Special Interface Standards
These pins are individual user-I/O pins unless collectively
they supply an input reference voltage, VREF_#, for any
SSTL, HSTL, GTL, or GTLP I/Os implemented in the asso-
ciated I/O bank.
The ‘#’ character in the pin name represents an integer, 0
through 7, that indicates the associated I/O bank.
The VREF function becomes active for this pin whenever a
signal standard requiring a reference voltage is used in the
associated bank.
If used as a user I/O, then each pin behaves as an indepen-
dent I/O described in the I/O type section. If used for a ref-
erence voltage within a bank, then
all
VREF pins within the
bank must be connected to the same reference voltage.
Spartan-3 devices are designed and characterized to sup-
port certain I/O standards when VREF is connected to
+1.25V, +1.10V, +1.00V, +0.90V, +0.80V, and +0.75V.
During configuration, these pins behave exactly like
user-I/O pins.
Figure 4:
JTAG Port
Data In
Data Out
Mode Select
Clock
TDI
TMS
TCK
TDO
JTAG Port
DS099-4_04_042103
Table 9:
JTAG Pin Descriptions
Pin Name
Direction
TCK
Input
Description
Bitstream Generation Option
The BitGen option
TckPin
determines whether a weak pull-up
resistor, weak pull-down resistor or
no resistor is present.
The BitGen option
TdiPin
determines whether a weak pull-up
resistor, weak pull-down resistor or
no resistor is present.
The BitGen option
TmsPin
determines whether a weak pull-up
resistor, weak pull-down resistor or
no resistor is present.
The BitGen option
TdoPin
determines whether a weak pull-up
resistor, weak pull-down resistor or
no resistor is present.
Test Clock:
The TCK clock signal synchronizes all
boundary scan operations on its rising edge.
TDI
Input
Test Data Input:
TDI is the serial data input for all JTAG
instruction and data registers. This input is sampled on
the rising edge of TCK.
TMS
Input
Test Mode Select:
The TMS input controls the
sequence of states through which the JTAG TAP state
machine passes. This input is sampled on the rising
edge of TCK.
Test Data Output:
The TDO pin is the data output for
all JTAG instruction and data registers. This output is
sampled on the rising edge of TCK. The TDO output is
an active totem-pole driver and is not like the
open-collector TDO output on Virtex-II Pro FPGAs.
TDO
Output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000-4CPG132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQ208C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQ208I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQG208C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQG208I | Spartan-3 FPGA Family: Complete Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4CPG132I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4FG1156C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family : Complete Data Sheet |
| XC3S1000-4FG1156I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4FG320C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 1M GATES 17280 CELLS 630MHZ 1.2V 320FBGA - Trays |
| XC3S1000-4FG320I | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 1M GATES 17280 CELLS 630MHZ 1.2V 320FBGA - Trays |
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