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參數(shù)資料
| 型號： | WM8768 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | 24-bit, 192kHz 8-Channel DAC |
| 中文描述： | 24位，192kHz的8通道DAC |
| 文件頁數(shù)： | 8/38頁 |
| 文件大?。?/td> | 393K |
| 代理商： | WM8768 |
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WM8768
Production Data
w
PD Rev 4.1 March 2005
8
MASTER CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 DAC Master Clock Timing Requirements
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width
high
MCLK System clock pulse width
low
MCLK System clock cycle time
MCLK Duty cycle
Power-saving mode activated
Normal mode resumed
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
MCLKH
11
ns
t
MCLKL
11
ns
t
MCLKY
28
40:60
2
0.5
1000
60:40
10
1
ns
Us
After MCLK stopped
After MCLK re-started
MCLK
cycle
Table 1 Master Clock Timing Requirements
Note:
If MCLK period is longer than maximum specified above, power-saving mode is entered and DACs are powered down with
internal digital audio filters being reset. In this power-saving mode, all registers will retain their values and can be
accessed in the normal manner through the control interface. Once MCLK is restored, the DACs are automatically
powered up, but a write to the volume update register bit is required to restore the correct volume settings.
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
DIN1/2/3/4
LRCLK
WM8768
DAC
DSP/
DECODER
4
Figure 2 Audio Interface - Master Mode
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| WM8768GEDS | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:24-bit, 192kHz 8-Channel DAC |
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