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參數(shù)資料
| 型號： | WM8768 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | 24-bit, 192kHz 8-Channel DAC |
| 中文描述： | 24位，192kHz的8通道DAC |
| 文件頁數(shù)： | 14/38頁 |
| 文件大小： | 393K |
| 代理商： | WM8768 |
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WM8768
Production Data
w
PD Rev 4.1 March 2005
14
SYSTEM CLOCK FREQUENCY (MHZ)
SAMPLING RATE
(LRCLK)
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
32kHz
44.1kHz
48kHz
96kHz
192kHz
4.096
5.6448
6.144
12.288
24.576
6.144
8.467
9.216
18.432
36.864
8.192
11.2896
12.288
24.576
Unavailable
12.288
16.9340
18.432
36.864
Unavailable
16.384
22.5792
24.576
Unavailable
Unavailable
24.576
33.8688
36.864
Unavailable
Unavailable
36.864
Unavailable
Unavailable
Unavailable
Unavailable
Table 6 System Clock Frequencies Versus Sampling Rate
HARDWARE CONTROL MODES
When the MODE pin is held high, the following hardware modes of operation are available.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes, the MUTE pin controls the selection of MUTE directly, and
can be used to enable and disable the automute function. This pin becomes an output when left
floating and indicates infinite zero detect (IZD) has been detected.
DESCRIPTION
0
1
Normal Operation
Mute DAC channels
Enable IZD, MUTE pin becomes an output to indicate when IZD occurs.
L=IZD not detected, H=IZD detected.
Floating
Table 7 Mute and Automute Control
Figure 9 shows the application and release of MUTE whilst a full amplitude sinusoid is being played
at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to
decay exponentially from the DC level of the last input sample. The output will decay towards V
MID
with a time constant of approximately 64 input samples. When MUTE is de-asserted, the output will
restart almost immediately from the current input sample.
Figure 9 Application and Release of Soft Mute
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
0
0.001
0.002
0.003
0.004
0.005
0.006
Time(s)
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