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參數(shù)資料
| 型號(hào)： | WED416S16030A10SI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | TSOP2-54 |
| 文件頁(yè)數(shù)： | 25/26頁(yè) |
| 文件大?。?/td> | 398K |
| 代理商： | WED416S16030A10SI |
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White Electronic Designs Corporation Westborough MA (508) 366-5151
White Electronic Designs
WED416S16030A
Current State
Command
Action
Notes
CE
RAS CAS
WE BA0,1
A11-12,
Description
A10/AP-A0
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
4
Write with
L
H
BA
Row Address
Bank Activate
ILLEGAL
4
Auto Precharge
L
H
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
L
X
Burst Termination
ILLEGAL
L
H
X
No Operation
Continue the Burst
H
X
Device Deselect
Continue the Burst
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
No Operation; Bank(s) idle after tRP
L
H
BA
Row Address
Bank Activate
ILLEGAL
4
Precharging
L
H
L
BA
Column
Write w/o Precharge
ILLEGAL
4
L
H
L
H
BA
Column
Read w/o Precharge
ILLEGAL
4
L
H
L
X
Burst Termination
No Operation; Bank(s) idle after tRP
L
H
X
No Operation
No Operation; Bank(s) idle after tRP
H
X
Device Deselect
No Operation; Bank(s) idle after tRP
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
4
L
H
BA
Row Address
Bank Activate
ILLEGAL
4,10
Row Activating
L
H
L
BA
Column
Write
ILLEGAL
4
L
H
L
H
BA
Column
Read
ILLEGAL
4
L
H
L
X
Burst Termination
No Operation; Row active after tRCD
L
H
X
No Operation
No Operation; Row active after tRCD
H
X
Device Deselect
No Operation; Row active after tRCD
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
4
L
H
BA
Row Address
Bank Activate
ILLEGAL
4
Write Recovering
L
H
L
BA
Column
Write
Start Write; Determine if Auto Precharge
9
L
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
9
L
H
L
X
Burst Termination
No Operation; Row active after tDPL
L
H
X
No Operation
No Operation; Row active after tDPL
H
X
Device Deselect
No Operation; Row active after tDPL
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
4
Write Recovering
L
H
BA
Row Address
Bank Activate
ILLEGAL
4
with Auto
L
H
L
BA
Column
Write
ILLEGAL
4,9
Precharge
L
H
L
H
BA
Column
Read
ILLEGAL
4,9
L
H
L
X
Burst Termination
No Operation; Precharge after tDPL
L
H
X
No Operation
No Operation; Precharge after tDPL
H
X
Device Deselect
No Operation; Precharge after tDPL
CURRENT STATE TRUTH TABLE (CONT.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED416S16030C10SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C75SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C7SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C8SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S8030A | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2Mx16x 4 Banks Synchronous DRAM |
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