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參數(shù)資料
| 型號： | WED416S16030A10SI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | TSOP2-54 |
| 文件頁數(shù)： | 18/26頁 |
| 文件大?。?/td> | 398K |
| 代理商： | WED416S16030A10SI |
25
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED416S16030A
FIG. 16 MODE REGISTER SET
CYCLE
NOTES:
Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
1. CE, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
FIG. 17 AUTO REFRESH CYCLE
RAS
CAS
ADDR
DQM
CKE
CLOCK
CE
Ra
Key
DQ
New Command
New
Command
Auto Refresh
MRS
WE
012
3
4
567
8
0
12
34
5
6
78
9
10
DON'T CARE
tRFC
HI-Z
Note 2
Note 1
Note 3
HIGH
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