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參數(shù)資料
| 型號(hào)： | WED416S16030A10SI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | TSOP2-54 |
| 文件頁數(shù)： | 15/26頁 |
| 文件大?。?/td> | 398K |
| 代理商： | WED416S16030A10SI |
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White Electronic Designs Corporation Westborough MA (508) 366-5151
White Electronic Designs
WED416S16030A
FIG. 13 BURST READ SINGLE BIT WRITE CYCLE @ BURST
LENGTH=2
NOTES:
1. BRSW mode is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1"
regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed
at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge.
RAS
CAS
ADDR
BA
DQM
A10/AP
CKE
CLOCK
CE
CBc
CAd
RBb
CAa
RAa
CL = 2
Row Active
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Write with
Auto Precharge
(B-Bank)
Precharge
(Both Banks)
Write
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
RAa
QAb0 QAb1
DBc0
QAd0 QAd1
DAa0
DON'T CARE
CAb
Note 2
RBb
RAc
CL = 3
DQ
QAb0 QAb1
DBc0
QAd0 QAd1
DAa0
Note 1
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| WED416S16030C10SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
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| WED416S8030A | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2Mx16x 4 Banks Synchronous DRAM |
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