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參數(shù)資料
| 型號(hào)： | WED416S16030A10SI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | TSOP2-54 |
| 文件頁數(shù)： | 12/26頁 |
| 文件大?。?/td> | 398K |
| 代理商： | WED416S16030A10SI |
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White Electronic Designs Corporation Westborough MA (508) 366-5151
White Electronic Designs
WED416S16030A
Symbol
Type
Signal
Polarity
Function
CLK
Input
Pulse
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating
the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CE
Input
Pulse
Active Low CE disable or enable device operation by masking or enabling all inputs except CLK, CKE and DQM.
RAS, CAS
Input
Pulse
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation
WE
to be executed by the SDRAM.
BA0,BA1
Input
Level
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-12 defines the row address (RA0-12) when sampled
A0-12,
at the rising clock edge.
A10/AP
Input
Level
During a Read or Write command cycle, A0-8 defines the column address (CA0-8) when sampled
at the rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge
operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected
and BA0, BA1 defines the bank to be precharged . If A10/AP is low, autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control
which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the
state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge.
DQ0-15
Input/Output Level
Data Input/Output are multiplexed on the same pins
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled
L(U)DQM
Input
Pulse
Mask
high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an
Active High output enable. In Write mode, DQM has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the Write operation if DQM is high.
VDD, Vss Supply
Power and ground for the input buffers and the core logic.
VDDQ, VSSQ Supply
Isolated power and ground for the output buffers to improve noise immunity.
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
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