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參數資料
| 型號： | WED416S16030A10SI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | TSOP2-54 |
| 文件頁數： | 13/26頁 |
| 文件大?。?/td> | 398K |
| 代理商： | WED416S16030A10SI |
20
White Electronic Designs Corporation Westborough MA (508) 366-5151
White Electronic Designs
WED416S16030A
FIG. 11 READ INTERRUPTED BY PRECHARGE COMMAND & READ
BURST STOP @ BURST LENGTH=FULL PAGE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated in above timing diagram. See the
label 1, 2. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer to the timing diagram of "Full page write
burst stop cycle."
3. Burst stop is valid at every burst length.
RAS
CAS
ADDR
BA
DQM
A10/AP
CKE
CLOCK
CE
CAb
CAa
RAa
CL = 2
Precharge
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
DON'T CARE
RAa
QAa0 QAa1 QAa2 QAa3 QAa4
QAb1
QAb0
QAb3
QAb2
QAb5
QAb4
CL = 3
DQ
QAa0 QAa1 QAa2 QAa3 QAa4
QAb1
QAb0
QAb3
QAb2
QAb5
QAb4
Note 2
1
2
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