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參數(shù)資料
| 型號(hào)： | WED416S16030A10SI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | TSOP2-54 |
| 文件頁(yè)數(shù)： | 22/26頁(yè) |
| 文件大?。?/td> | 398K |
| 代理商： | WED416S16030A10SI |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED416S16030A
CKE
Command
Previous Current
CE
RAS
CAS
WE
DQM
BA0,1 A10/Ap A0-9, A11-12 Notes
Cycle
Register
Mode Register Set
H
X
L
X
OP CODE
Refresh
Auto(CBR)
H
LLL
H
X
Entry Self
L
Precharge
Single Bank
HX
L
H
L
X
BA
L
X
2
All Banks
XH
X
Bank Activate
H
X
L
H
X
BA
Row Address
2
Write
Auto Precharge Disable
H
X
LHL
L
X
BA
L
Column
2
Auto Precharge Enable
H
Address
2
Read
Auto Precharge Disable
H
X
LHL
H
X
BA
L
Column
2
Auto Precharge Enable
H
Address
2
Burst Stop
H
X
L
H
L
X
3
No Operation
H
X
L
H
X
Device Select
H
X
H
X
Clock Suspend/Standby Mode
L
X
4
Data
Write/Output Enable
H
X
XXX
X
L
XX
X
5
Mask/Output Disable
H
5
Power Down Mode
Entry
X
L
H
X
XX
X
6
Exit
H
6
NOTES:
1. All of the SDRAM operations are defined by states of CE, WE, RAS, CAS, and DQM at the positive rising edge of the clock.
2. Bank Select (BA), if BA0, BA1 = 0, 0 then bank A is selected, if BA0, BA1 = 1, 0 then bank B, if BA0, BA1 = 0, 1 then bank C, if BA0, BA1 = 1,
1 then bank D is selected, respectively.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and
Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data
outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it
activates, the Write operation at the clock is prohibted (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not perform any Refresh operations,
therefore the device cannot remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry
and exit.
COMMAND TRUTH TABLE
(X = Don't Care, H = Logic High, L = Logic Low)
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| WED416S16030C10SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C75SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C7SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C8SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S8030A | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2Mx16x 4 Banks Synchronous DRAM |
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