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參數(shù)資料
| 型號： | W942516BH |
| 英文描述： | DRAM |
| 中文描述： | 內(nèi)存 |
| 文件頁數(shù)： | 23/45頁 |
| 文件大?。?/td> | 1601K |
| 代理商： | W942516BH |
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W942508BH
Publication Release Date: March 19, 2002
- 23 -
Revision A1
Burst Termination
When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated.
When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after
clock cycle of (CAS latency) from the Precharge command. When the Burst Write cycle is interrupted
by the Precharge command . the input circuit is reset at the same clock cycle at which the precharge
command is issued. In this case, the DM signal must be asserted "high": during t
WR
to prevent writing
the invalided data to the cell array.
When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read
operation is terminated. The Burst read Stop command is not supported during a write burst operation.
Refer to the diagrams for Burst termination.
Refresh Operation
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By
repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation
must be performed 8192 times(rows) within 64 mS. The period between the Auto Refresh command
and the next command is specified by t
RFC
.
Self Refresh mode enter issuing the Self Refresh command (CKE asserted "low"). while all banks are
in the idle state. The device is in Self Refresh mode for as long as cke held "low". In the case of 8192
burst Auto Refresh commands, 8192 burst Auto Refresh commands must be performed within 7.8
μ
S
before entering and after exiting the Self Refresh mode. In the case of distributed Auto Refresh
commands, distributed auto refresh commands must be issued every 7.8
μ
S and the last distributed
Auto Refresh commands must be performed within 7.8
μ
S before entering the self refresh mode. After
exiting from the Self Refresh mode, the refresh operation must be performed within 7.8
μ
S. In Self
Refresh mode, all input/output buffers are disable, resulting in lower power dissipation (except CKE
buffer). Refer to the diagrams for Refresh operation.
Power Down Mode
Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode
and Precharge Standby Power Down Mode.
When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting
in low power dissipation (except CKE buffer).
Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking
CKE: "high" can exit this mode. When CKE goes high, a No operation command must be input at next
CLK rising edge. Refer to the diagrams for Power Down Mode.
Mode Register Operation
The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks
are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12 and
BS0, BS1 address inputs.
The Mode Register designates the operation mode for the read or write cycle. The register is divided
into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to
designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time
in clock cycle (4) DLL reset field to reset the dll (5) Regular/Extended Mode Register filed to select a
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