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參數(shù)資料
| 型號： | W942516BH |
| 英文描述： | DRAM |
| 中文描述： | 內存 |
| 文件頁數(shù)： | 20/45頁 |
| 文件大?。?/td> | 1601K |
| 代理商： | W942516BH |
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W942508BH
- 20 -
The write command performs a Write operation to the bank designated by BS. The write data are
latched at both edges of DQS. The length of the write data (Burst Length) and column access
sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write
operation.
5. Write with Auto Precharge Command
(RAS ="H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10= "H", A0 to A9, A11 = Column Address)
The Write with Auto Precharge command performs the Precharge operation automatically after the
Write operation. This command must not be interrupted by any other commands.
6. Read Command
(RAS ="H", CAS = "L", WE = "H", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11 = Column
Address)
The Read command performs a Read operation to the bank designated by BS. The read data are
synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode
and CAS Latency (access time from CAS command in a clock cycle) must be programmed in
the Mode Register at power-up prior to the Read operation.
7. Read with Auto Precharge Command
(RAS = "H", CAS = "L", WE = "H", BS0, BS1 = Bank, A10 = "H", A0 to A9, A11 = Column
Address)
The Read with Auto precharge command automatically performs the Precharge operation after the
Read operation.
1) READA
≥
t
RAS (min)
- (BL/2) x t
CK
Internal precharge operation begins after BL/2 cycle from Read with Auto Precharge command.
2) t
RCD(min)
≤
READA < t
RAS(min)
- (BL/2) x t
CK
Data can be read with shortest latency, but the internal Precharge operation does not begin until
after t
RAS (min)
has completed.
This command must not be interrupted by any other command.
8. Mode Register Set Command
(RAS = "L", CAS = "L", WE = "L", BS0 = "L", BS1 = "L", A0 to A12 = Register Data)
The Mode Register Set command programs the values of CAS latency, Addressing Mode, Burst
Length and DLL reset in the Mode Register. The default values in the Mode Register after power-
up are undefined, therefore this command must be issued during the power-up sequence. Also,
this command can be issued while all banks are in the idle state. Refer to the table for specific
codes.
9. Extended Mode Register Set Command
(RAS = "L", CAS = "L", WE = "L", BS0 = "H", BS1 = "L", A0 to A12 = Register data)
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| W9425G6EH-5 | 功能描述:IC DDR-400 SDRAM 256MB 66TSSOPII RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應商設備封裝:8-MFP 包裝:帶卷 (TR) |
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