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參數(shù)資料
| 型號： | W28J161BB90L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | 8 X 8 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件頁數(shù)： | 9/43頁 |
| 文件大?。?/td> | 1333K |
| 代理商： | W28J161BB90L |
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W28J161B/T
Publication Release Date: April 7, 2003
- 17 -
Revision A4
When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The CUI will remain in read status register mode until
a new command is issued.
This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set.
An invalid Set Block or Permanent Lock-Bit command will result in status register bits SR.4 and SR.5
being set to "1". Also, reliable operations occur only when VDD = 2.7V to 3.6V and VPP = VPPH1/2. In the
absence of this high voltage, lock-bit contents are protected against alteration.
A successful set block lock-bit operation requires that the permanent lock-bit be cleared. If it is
attempted with the permanent lock-bit set, SR.1 and SR.4 will be set to "1" and the operation will fail.
Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. If the permanent
lock-bit is not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the
permanent lock-bit is set, block lock-bits cannot be cleared. See Table 5 for a summary of hardware
and software write protection options.
Clear block lock-bits operation is executed by a two-cycle command sequence. A clear block lock-bits
setup is first written. After the command is written, the device automatically outputs status register
data when read (see Figure 11). The CPU can detect completion of the clear block lock-bits event by
reading the status register bit SR.7.
When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register
bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur
when VDD = 2.7V to 3.6V and VPP = VPPH1/2. If a clear block lock-bits operation is attempted while VPP ≤
VPPLK, SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bits content
are protected against alteration. A successful clear block lock-bits operation requires that the
permanent lock-bit is not set. If it is attempted with the permanent lock-bit set, SR.1 and SR.5 will be
set to "1" and the operation will fail.
If a clear block lock-bits operation is aborted due to VPP or VDD transitioning out of valid range or
#RESET active transition, block lock-bit values are left in an undetermined state. A repeat of clear
block lock-bits is required to initialize block lock-bit contents to known values. Once the permanent
lock-bit is set, it cannot be cleared.
Block Locking by the #WP
This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the
kernel code for the system can be kept secure while other blocks are programmed or erased as
necessary.
The lockable two boot blocks are locked when #WP = VIL; any program or erase operation to a locked
block will result in an error, which will be reflected in the status register. For top configuration, the top
two boot blocks are lockable. For the bottom configuration, the bottom two boot blocks are lockable. If
#WP is VIH and block lock-bit is not set, boot block can be programmed or erased normally (Unless
VPP is below VPPLK). #WP is valid only two boot blocks, other blocks are not affected.
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