參數(shù)資料
型號(hào)： W28J161BB90L
廠商： WINBOND ELECTRONICS CORP
元件分類(lèi)： PROM
英文描述： 1M X 16 FLASH 3V PROM, 90 ns, PBGA48
封裝： 8 X 8 MM, 0.75 MM PITCH, TFBGA-48
文件頁(yè)數(shù)： 26/43頁(yè)
文件大?。?/td> 1333K
代理商： W28J161BB90L
W28J161B/T
- 32 -
DC Characteristics (Continued)
VDD = 2.7V - 3.6V
PARAMETER
SYM.
TEST
CONDITIONS
Min.
Max.
UNIT
Input Low Voltage (note 6)
VIL
-0.5
0.8
V
Input High Voltage (note 6)
VIH
2.0
VDD +0.5
V
Output Low Voltage (note 6)
VOL
VDD = VDD Min.
IOL = 2.0 mA
0.4
V
Output High Voltage (TTL) (note 6)
VOH1
VDD = VDD Min.
IOH = -2.0 mA
2.4
V
0.85 VDD
V
Output High Voltage (CMOS) (note 6)
VOH2
VDD = VDD Min.
IOH = -2.5 mA
VDD -0.4
V
VPP Lockout during Normal Operations
(note 3, 6)
VPPLK
VDD = VDD Min.
IOH = -100
A
1.0
V
VPP during Block Erase, Full Chip Erase, Word
Write or Lock-Bit Configuration Operations
VPPH1
2.7
3.6
V
VPP during Block Erase, Full Chip Erase, Word
Write or Lock-Bit Configuration Operations
(note 7)
VPPH2
11.7
12.3
V
VDD Lockout Voltage
VLKO
2.0
V
Notes:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VDD voltage and TA = +25° C.
2. ICCWS and ICCES are specified with the device de-selected. If read or word written while in erase suspend mode, the device’s
current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively.
3. Block erases, full chip erase, word writes and lock-bit configurations are inhibited when VPP ≤ VPPLK, and not guaranteed in
the range between VPPLK (max.) and VPPH1 (min.), between VPPH1(max.) and VPPH2 (min.) and above VPPH2(max.).
4. The Automatic Power Savings (APS) feature is placed automatically power save mode that addresses not switching more
than 300ns while read mode.
5. About all of pin except describe Test Conditions, CMOS level inputs are either VDD ±0.2V or VSS ±0.2V, TTL level inputs are
either VIL or VIH.
6. Sampled, not 100% tested.
7. Applying 12V
±0.3V to VPP during erase/write can only be done for a maximum of 1000 cycles on each block. VPP may be
connected to 12V
±0.3V for a total of 80 hours maximum.
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