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參數(shù)資料
| 型號： | W28J161BB90L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | 8 X 8 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件頁數(shù)： | 19/43頁 |
| 文件大小： | 1333K |
| 代理商： | W28J161BB90L |
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W28J161B/T
- 26 -
Bus Operation
Command
Comments
Write
Read Status
Register
Data = 70H
Addr = X
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write
Clear Block
Lock-Bits
Setup
Data = 60H
Addr = X
Write
Clear Block
Lock-Bits
Confirm
Data = D0H
Addr = X
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write FFH after the Clear Block Lock-Bits operation to
place device in read array mode.
Start
Write 70H
SR.7=
Write 60H
Read Status
Register
SR.7=
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
Read Status
Register
Write D0H
1
0
1
0
Full STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
SR.3=
SR.1=
SR.4,5=
SR.5=
Clear Block Lock-Bits
0
1
Vpp Range Error
Device Protect Error
Command Sequence
Clear Block Lock-Bits Error
Error
Successfully
Bus Operation
Command
Comments
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
Permanent Lock-Bit is Set
Standby
Check SR.4, 5
Both 1 = Command
Sequence Error
Standby
Check SR.5
1 = Clear Block Lock-Bits
Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command. If error is detected, clear the
Status Register before attempting retry or other error
recovery.
Figure 11. Clear Block Lock-Bits Flowchart
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