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參數(shù)資料
| 型號： | W28J161BB90L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | 8 X 8 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件頁數(shù)： | 34/43頁 |
| 文件大?。?/td> | 1333K |
| 代理商： | W28J161BB90L |
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W28J161B/T
- 4 -
3. PRODUCT OVERVIEW
The W28J161B/T is a high-performance 16M-bit Boot Block Flash memory organized as 1M-word of
16 bits. The 1M-word of data is arranged in two 4k-word boot blocks, six 4k-word parameter blocks
and thirty-one 32k-word main blocks which are individually erasable, lockable and unlockable in-
system. The memory map is shown in Figure 3.
The dedicated VPP pin gives complete data protection when VPP ≤ VPPLK. A Command User Interface
(CUI) serves as the interface between the system processor and internal operation of the device. A
valid command sequence written to the CUI initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms and timings necessary for block erase, full chip
erase, word write and lock-bit configuration operations.
A block erase operation erases one of the device’s 32k-word blocks typically within 1.2s (3V VDD, 3V
VPP), 4k-word blocks typically within 0.6s (3V VDD, 3V VPP) independent of other blocks. Each block
can be independently erased minimum 100,000 times. Block erase suspend mode allows system
software to suspend block erase to read or write data from any other block.
Writing memory data is performed in word increments of the device’s 32k-word blocks typically within
33
S (3V VDD, 3V VPP), 4k-word blocks typically within 36 S (3V VDD, 3V VPP). Word write suspend
mode enables the system to read data or execute code from any other flash memory array location.
Individual block locking uses a combination of bits, thirty-nine block lock-bits, a permanent lock-bit and
#WP pin, to lock and unlock blocks. Block lock-bits gate block erase, full chip erase and word write
operations, while the permanent lock-bit gates block lock-bit modification and locked block alternation.
Lock-bit configuration operations (Set Block Lock-Bit, Set Permanent Lock-Bit and Clear Block Lock-
Bits commands) set and cleared lock-bits.
The status register indicates when the WSM’s block erase, full chip erase, word write or lock-bit
configuration operation is finished.
The access time is 90 nS (tAVQV) over the operating temperature range (-40° C to +85° C) and VDD
supply voltage range of 2.7V to 3.6V.
The Automatic Power Savings (APS) feature substantially reduces active current when the device is in
static mode (addresses not switching). In APS mode, the typical ICCR current is 2 A (CMOS) at 3.0V
VDD.
When #CE and #RESET pins are at VDD, the ICC CMOS standby mode is enabled. When the #RESET
pin is at VSS, reset mode is enabled which minimizes power consumption and provides write
protection. A reset time (tPHQV) is required from #RESET switching high until outputs are valid.
Likewise, the device has a wake time (tPHEL) from #RESET-high until writes to the CUI are recognized.
With #RESET at VSS, the WSM is reset and the status register is cleared.
Overwriting a "0" to a bit already holding a data "0" may render this bit un-erasable. In order to avoid
this potential "stuck bit" failure, when re-programming (changing data from "1" to "0") the following
should be followed:
Program "0" for the bit in which you want to change data from "1" to "0".
Program "1" for the bit which is already holding a data "0". (Note: Since only an erase process
can change the data from "0" to "1", programming "1" to a bit holding a data "0" will not
change the data).
For example, changing data from "10111101" to "10111100" requires "11111110" programming.
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