參數(shù)資料
型號(hào)： W28J161BB90L
廠商： WINBOND ELECTRONICS CORP
元件分類(lèi)： PROM
英文描述： 1M X 16 FLASH 3V PROM, 90 ns, PBGA48
封裝： 8 X 8 MM, 0.75 MM PITCH, TFBGA-48
文件頁(yè)數(shù)： 20/43頁(yè)
文件大小： 1333K
代理商： W28J161BB90L
W28J161B/T
Publication Release Date: April 7, 2003
- 27 -
Revision A4
10. DESIGN CONSIDERATIONS
Three-Line Output Control
This device will often be used in large memory arrays. Winbond provides three control inputs to
accommodate multiple memory connections. Three-line control provides for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not occur.
To use these control inputs efficiently, an address decoder should enable #CE while #OE should be
connected to all memory devices and the system’s #READ control line. This assures that only
selected memory devices have active outputs while deselected memory devices are in standby mode.
#RESET should be connected to the system POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD should also toggle during system reset.
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers
are interested in three supply current issues; standby current levels, active current levels and transient
peaks produced by falling and rising edges of #CE and #OE. Transient current magnitudes depend on
the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. Each device should have a 0.1
F ceramic capacitor
connected between VDD and VSS and between VPP and VSS. These high-frequency, low inductance
capacitors should be placed as close as possible to package leads. Additionally, for every eight
devices, a 4.7
F electrolytic capacitor should be placed at the array’s power supply connection
between VDD and VSS. The bulk capacitor will overcome voltage drops caused by PC board trace
inductance.
VPP Trace on Printed Circuit Boards
Updating flash memories that reside in the target system requires that the printed circuit board
designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for
word writing and block erasing. Use similar trace widths and layout considerations given to the VDD
power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and
overshoots.
VDD, VPP, #RESET Transitions
Block erase, full chip erase, word write and lock-bit configuration are not guaranteed if VPP falls
outside of a valid VPPH1/2 range, VDD falls outside of a valid 2.7V to 3.6V range, or #RESET ≠ VIH. If VPP
error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the
attempted operation. If #RESET transitions to VIL during block erase, full chip erase, word write or
lock-bit configuration, SR.7 will remain "0" until the reset operation is complete. Then, the operation
will abort and the device will enter reset mode. The aborted operation may leave data partially altered.
Therefore, the command sequence must be repeated after normal operation is restored. Device
power-off or #RESET transitions to VIL clear the status register.
The CUI latches commands issued by system software and is not altered by VPP or #CE transitions or
WSM actions. Its state is read array mode upon power-up, after exit from reset mode or after VDD
transitions below VLKO.
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