參數(shù)資料
型號(hào)： W19B320BTT-H
廠商： WINBOND ELECTRONICS CORP
元件分類(lèi)： PROM
英文描述： 2M X 16 FLASH 3V PROM, 70 ns, PDSO48
封裝： TSOP-48
文件頁(yè)數(shù)： 5/56頁(yè)
文件大小： 0K
代理商： W19B320BTT-H
W19B320BT/B DATASHEET
Publication Release Date:Dec. 25, 2007
- 13 -
Revisionv A3
Write the three-cycle Enter Security Sector Region command sequence, and then follow the
in-system sector protect algorithm, except that #RESET may be at either V IH or VID. This
allows in-system protection of the Security Sector without raising any device pin to a high
voltage.
Please note that this method is only suitable for the Security Sector.
To verify the protect/unprotect status of the Security Sector; follow the algorithm show in
Security Sector Protect Verify.
The Security Sector protection must be used with caution, since there is no procedure available for
unprotect the Security Sector area and none of the bits in the Security Sector memory space can be
modified in any ways.
6.1.13 Hardware Data Protection
The command sequence requirements of unlock cycles for programming or erasing provides data
protection against negligent writes. In addition, the following hardware data protection measures
prevent inadvertent erasure or programming, which might be caused by spurious system level signals
during VDD power-up and power-down transitions, or from system noise.
Write Pulse “Glitch” Protection
Noise pulses, which is less than 5 ns (typical) on #OE, #CE or #WE, do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of #OE = VIL, #CE = VIH or #WE = VIH. #CE and #WE
must be a logical zero while #OE is a logical one to initiate a write cycle.
Power-Up Write Inhibit
During power up, if #WE = #CE = VIL and #OE = VIH, the device does not accept commands on the
rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up.
6.2 Command Definitions
The device operation can be initiated by writing specific address and data commands or sequences
into the command register. The device will be reset to reading array data when writing incorrect
address and data values or writing them in the improper sequence.
The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the
data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing
waveforms.
6.2.1
Reading Array Data
After device power-up, it is automatically set to reading array data. There is no commands are
required to retrieve data. After completing an Embedded Program or Embedded Erase algorithm,
each bank is ready to read array data.
After the device accepts an Erase Suspend command, the corresponding bank enters the erase-
suspend-read mode. After it the system can read data from any non-erase-suspended sector within
the same bank. And then, after completing a programming operation in the Erase Suspend mode, the
system may once again read array data with the same exception. Please refer to Erase
Suspend/Erase Resume Commands section for detail information.
相關(guān)PDF資料
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