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參數(shù)資料
| 型號： | W127 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 200K |
| 代理商： | W127 |
W127/W127-A
PRELIMINARY
Document #: 38-07225 Rev. *A
Page 6 of 20
Serial Data Interface
The W127/W127-A features a two-pin, serial data interface
that can be used to configure internal register settings that
control particular device functions. Upon power-up, the
W127/W127-A initializes with default register settings, there-
fore the use of this serial data interface is optional. The serial
interface is write-only (to the clock chip) and is the dedicated
function of device pins SDATA and SCLOCK. In motherboard
applications, SDATA and SCLOCK are typically driven by two
logic outputs of the chipset. Clock device register changes are
normally made upon system initialization, if any are required.
The interface can also be used during system operation for
power management functions.
Table 5
summarizes the control
functions of the serial data interface.
Operation
Data is written to the W127/W127-A in ten bytes of eight bits
each. Bytes are written in the order shown in
Table 6
.
Table 5. Serial Data Interface Control Functions Summary
Control Function
Clock Output Disable
Any individual clock output(s) can be disabled. Dis-
abled outputs are actively held LOW.
Description
Common Application
Unused outputs are disabled to reduce EMI
and system power. Examples are clock out-
puts to unused SDRAM DIMM socket or PCI
slot.
For alternate CPU devices and power man-
agement options. Smooth frequency transi-
tion allows CPU frequency change under nor-
mal system operation.
Production PCB testing.
No user application. Register bit must be writ-
ten as 0.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections. Frequen-
cy is changed in a smooth and controlled fashion.
Output Three-state
(Reserved)
Puts all clock outputs into a high-impedance state.
Reserved function for future device revision or pro-
duction device testing.
Table 6. Byte Writing Sequence
Byte Sequence
1
Byte Name
Slave Address
Bit Sequence
11010010
Byte Description
Commands the W127/W127-A to accept the bits in Data Bytes 0
–
6 for
internal register configuration. Since other devices may exist on the
same common serial data bus, it is necessary to have a specific slave
address for each potential receiver. The slave receiver address for the
W127/W127-A is 11010010. Register setting will not be made if the
Slave Address is not correct (or is for an alternate slave receiver).
Unused by the W127/W127-A, therefore bit values are ignored (
“
don
’
t
care
”
). This byte must be included in the data write sequence to maintain
proper byte allocation. The Command Code Byte is part of the standard
serial communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
Unused by the W127/W127-A, therefore bit values are ignored (
“
don
’
t
care
”
). This byte must be included in the data write sequence to maintain
proper byte allocation. The Byte Count Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
The data bits in these bytes set internal W127/W127-A registers that
control device operation. The data bits are only accepted when the Ad-
dress Byte bit sequence is 11010010, as noted above. For description
of bit control functions, refer to
Table 7
, Data Byte Serial Configuration
Map.
2
Command
Code
Don
’
t Care
3
Byte Count
Don
’
t Care
4
5
6
7
8
9
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Refer to
Table 7
10
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