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參數(shù)資料
| 型號： | W127 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 200K |
| 代理商： | W127 |
W127/W127-A
PRELIMINARY
Document #: 38-07225 Rev. *A
Page 15 of 20
AC Electrical Characteristics
(continued)
SDRAM Clock Outputs, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)
Parameter
t
P
f
t
R
t
F
t
D
t
JC
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
Measured on rising edge at 1.5V
CPU = 66.6 MHz
Min.
Typ.
15
66.6
1
1
45
Unit
ns
MHz
V/ns
V/ns
%
ps
Max.
Period
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
4
4
55
250
t
SK
t
SK
Output Skew
CPU to SDRAM Clock Skew Covers all CPU/SDRAM outputs. Measured on
rising edge at 1.5V.
Frequency Stabilization from
Power-up (cold start)
from power-up. Short cycles exist prior to frequen-
cy stabilization.
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
100
ps
ps
500
f
ST
Assumes full supply voltage reached within 1 ms
3
ms
Z
o
10
15
20
PCI Clock Outputs, PCI_F and PCI0:4 (Lump Capacitance Test Load = 30 pF)
Parameter
t
P
f
t
H
t
L
t
R
t
F
t
D
t
JC
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
Measured on rising edge at 1.5V
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequen-
cy stabilization.
Average value during switching transition. Used
for determining series termination value.
CPU = 66.6 MHz
Min.
Typ.
30
33.3
12
12
1
1
45
Unit
ns
MHz
ns
ns
V/ns
V/ns
%
ps
Max.
Period
Frequency, Actual
High Time
Low Time
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
4
4
55
250
t
SK
t
O
Output Skew
AGP to PCI Clock Skew
250
3
ps
ns
1
f
ST
Frequency Stabilization from
Power-up (cold start)
3
ms
Z
o
AC Output Impedance
20
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