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參數(shù)資料
| 型號： | W127 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 200K |
| 代理商： | W127 |
W127/W127-A
PRELIMINARY
Document #: 38-07225 Rev. *A
Page 10 of 20
How To Use the Serial Data Interface
Electrical Requirements
Figure 5
illustrates electrical characteristics for the serial inter-
face bus used with the W127/W127-A. Devices send data over
the bus with an open drain logic output that can (a) pull the bus
line LOW, or (b) let the bus default to logic 1. The pull-up re-
sistors on the bus (both clock and data lines) establish a de-
fault logic 1. All bus devices generally have logic inputs to re-
ceive data.
Although the W127/W127-A is a receive-only device (no data
write-back capability), it does transmit an
“
acknowledge
”
data
pulse after each byte is received. Thus, the SDATA line can
both transmit and receive data.
The pull-up resistor should be sized to meet the rise and fall
times specified in AC parameters, taking into consideration
total bus line capacitance.
DATA IN
DATA OUT
N
CLOCK IN
CLOCK OUT
CHIP SET
(SERIAL BUS MASTER TRANSMITTER)
SDCLK
SDATA
SERIAL BUS CLOCK LINE
SERIAL BUS DATA LINE
N
DATA IN
DATA OUT
CLOCK IN
CLOCK DEVICE
(SERIAL BUS SLAVE RECEIVER)
SCLOCK
SDATA
N
~ 2k
~ 2k
VDD
VDD
Figure 5. Serial Interface Bus Electrical Characteristics
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