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參數(shù)資料
| 型號： | W127 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 200K |
| 代理商： | W127 |
W127/W127-A
PRELIMINARY
Document #: 38-07225 Rev. *A
Page 11 of 20
Signaling Requirements
As shown in
Figure 6
, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
pulse. A transitioning data line during a clock HIGH pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
A write sequence is initiated by a
“
start bit
”
as shown in
Figure
7
. A
“
stop bit
”
signifies that a transmission has ended.
As stated previously, the W127/W127-A sends an
“
acknowl-
edge
”
pulse after receiving eight data bits in each byte as
shown in
Figure 8
.
SDATA
SCLOCK
Valid
Data
Bit
Change
of Data Allowed
Figure 6. Serial Data Bus Valid Data Bit
SDATA
SCLOCK
Start
Bit
Stop
Bit
Figure 7. Serial Data Bus Start and Stop Bit
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