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參數(shù)資料
| 型號： | W127 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 200K |
| 代理商： | W127 |
W127/W127-A
PRELIMINARY
Document #: 38-07225 Rev. *A
Page 16 of 20
AC Electrical Characteristics
(continued)
REF Clock Output (Lump Capacitance Test Load = 45 pF)
Parameter
f
t
R
t
F
t
D
f
ST
Description
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition.
Used for determining series termination value.
CPU = 66.6 MHz
Min.
Typ.
14.31818
0.5
0.5
40
Unit
MHz
V/ns
V/ns
%
ms
Max.
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
2
2
60
1.5
Z
o
AC Output Impedance
30
48-/24-MHZ Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
f
Description
Test Condition/Comments
Determined by PLL divider ratio
(see m/n below)
(48.008
–
48)/48
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition.
Used for determining series termination value.
CPU = 66.6 MHz
Min.
Typ.
48.008/24.004
Unit
MHz
Max.
Frequency, Actual
f
D
m/n
t
R
t
F
t
D
f
ST
Deviation from 48 MHz
PLL Ratio
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
+167
ppm
57/17, 54/34
0.5
0.5
45
2
2
V/ns
V/ns
%
ms
55
3
Z
o
AC Output Impedance
30
0
Serial Input Port
Parameter
f
SCLOCK
t
STHD
t
LOW
t
HIGH
t
DSU
t
DHD
Description
Test Condition
Min.
0
4.0
4.7
4.0
250
0
Typ.
Max.
100
Unit
kHz
μs
μs
μs
SCLOCK Frequency
Start Hold Time
SCLOCK Low Time
SCLOCK High Time
Data Set-up Time
Data Hold Time
Normal Mode
ns
ns
(Transmitter should provide a 300-ns hold
time to ensure proper timing at the receiver.)
t
R
t
F
t
STSU
t
SPF
Rise Time, SDATA and SCLOCK From 0.3V
DD
to 0.7V
DD
Fall Time, SDATA and SCLOCK
Stop Set-up Time
Bus Free Time between Stop
and Start Condition
Allowable Noise Spike Pulse
Width
1000
300
ns
ns
μs
μs
From 0.7V
DD
to 0.3V
DD
4.0
4.7
t
SP
50
ns
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