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參數(shù)資料
| 型號： | W127 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 200K |
| 代理商： | W127 |
W127/W127-A
PRELIMINARY
Document #: 38-07225 Rev. *A
Page 4 of 20
CPU/PCI Frequency Selection
CPU output frequency is selected with I/O pins 8, 47, and 48.
Refer to
Table 1
for CPU/PCI frequency programming informa-
tion. Alternatively, frequency selections are available through
the serial data interface. Refer to
Table 8
,
“
Additional Frequen-
cy Selections through Serial Data Interface Data Bytes,
”
on
page 9.
Output Buffer Configuration
Clock Outputs
All clock outputs are designed to drive serially terminated clock
lines. The W127/W127-A outputs are CMOS-type, which pro-
vide rail-to-rail output swing.
Crystal Oscillator
The W127/W127-A requires one input reference clock to syn-
thesize all output frequencies. The reference clock can be ei-
ther an externally generated clock signal or the clock generat-
ed by the internal crystal oscillator. When using an external
clock signal, pin X1 is used as the clock input and pin X2 is left
open. The input threshold voltage of pin X1 is (V
DDQ3
)/2.
The internal crystal oscillator is used in conjunction with a
quartz crystal connected to device pins X1 and X2. This forms
a parallel resonant crystal oscillator circuit. The W127/W127-A
incorporates the necessary feedback resistor and crystal load
capacitors. Including typical stray circuit capacitance, the total
load presented to the crystal is approximately 20 pF. For opti-
mum frequency accuracy without the addition of external ca-
pacitors, a parallel-resonant mode crystal specifying a load of
20 pF should be used. This will typically yield reference fre-
quency accuracies within ±100 ppm. To achieve similar accu-
racies with a crystal calling for a greater load, external capac-
itors must be added such that the total load (internal, external,
and parasitic capacitors) equals that called for by the crystal.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Output
Low
Q
D
W127/W127-A
V
DDQ3
Clock Load
R
10 k
Output
Buffer
(Load Option 1)
10 k
(Load Option 0)
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Output
Low
Q
D
W127/W127-A
V
DD
Clock Load
R
10 k
Output
Buffer
Output Strapping Resistor
Series Termination Resistor
Jumper Options
Figure 2. Input Logic Selection Through Jumper Option
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