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參數(shù)資料
| 型號(hào)： | W127 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 2/20頁(yè) |
| 文件大小： | 200K |
| 代理商： | W127 |
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W127/W127-A
PRELIMINARY
Document #: 38-07225 Rev. *A
Page 2 of 20
Pin Definitions
Pin Name
CPU0:3
Pin
No.
44, 43,
41, 40
Pin
Type
O
Pin Description
CPU Clock Outputs 0 through 3:
These four CPU clock outputs are controlled
by the CPU_STOP# control pin. Output voltage swing is controlled by voltage
applied to VDDQ2.
Free-running PCI Clock Output and Frequency Selection Bit 2:
As an output,
this pin works in conjunction with PCI0:4. Output voltage swing is controlled by
voltage applied to VDDQ3.
When an input, this pin functions as part of the frequency selection address. The
value of FS0:2 determines the power-up default frequency of device output clocks
as per
Table 1
,
“
Pin Selectable Frequency
”
on page 1.
PCI Clock Outputs 0 through 4:
Output voltage swing is controlled by voltage
applied to VDDQ3. Outputs are held LOW if PCI_STOP# is set LOW.
SDRAM Clock Outputs:
These eight SDRAM clock outputs run synchronous to
the CPU clock outputs or AGP clock output as selected using SD_SEL per
Table 2
.
SDRAM Clock Outputs:
These four SDRAM clock outputs run synchronous to
the CPU clock outputs or AGP clock output as selected using SD_SEL per
Table
2
. If programmed as inputs, (refer to MODE pin description), these pins are used
for STOP_ CPU, AGP, PCI, and power-down control.
48-MHz Output and Frequency Selection Bit 1:
Fixed clock output that defaults
to 48 MHz following device power-up.
When an input, this pin functions as part of the frequency selection address. The
value of FS0:2 determines the power-up default frequency of device output clocks
as per
Table 1
,
“
Pin Selectable Frequency
”
on page 1.
24-MHz Output and Frequency Selection Bit 0:
Fixed clock output that defaults
to 24 MHz following device power-up.
When an input, this pin functions as part of the frequency selection address. The
value of FS0:2 determines the power-up default frequency of device output clocks
as per
Table 1
,
“
Pin Selectable Frequency
”
on page 1.
Free-running AGP Output and Mode Control Input:
As an output, this pin works
in conjunction with AGP0 and is a free running clock. When an input, it determines
the functions for pin 29, 30, 31, and 32. See
Table 3
.
AGP Output:
This output is controlled by the AGP_STOP# pin.
Fixed 14.318-MHz and SDRAM Output Selection:
As an output, this pin is used
for various system applications. Output voltage swing is controlled by voltage
applied to VDDQ3.
When an input, this pin selects the SDRAM to run synchronous to either CPU or
AGP. See
Table 2
.
Crystal Connection or External Reference Frequency Input:
This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
Crystal Connection:
An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Serial Data Input:
Data input for Serial Data Interface. Refer to Serial Data Inter-
face section that follows.
Serial Clock Input:
Clock input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
Power Connection:
Connected to 3.3V supply.
PCI_F/FS2
8
I/O
PCI0:4
9, 11, 12, 13,
14
38, 37, 35, 34,
27, 26, 21, 20
32, 31, 30, 29
O
SDRAM0:3
SDRAM8:11
SDRAM4:7
O
I/O
48MHZ/FS1
48
I/O
24MHZ/FS0
47
I/O
AGP_F/MODE
17
I/O
AGP0
REF/SD_SEL
18
3
O
I/O
X1
5
I
X2
6
I
SDATA
23
I
SCLOCK
25
I
VDDQ3
1, 2, 7, 19, 22,
24, 36
42
4, 10, 15, 16,
28, 33, 39, 45,
46
P
VDDQ2
GND
P
G
Power Connection:
Power Supply for CPU0:3 clock outputs. (3.3V Supply)
Ground Connection:
Connect all ground pins to the common system ground
plane.
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