參數(shù)資料
型號(hào)： VMX51C900
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 MCU with LCD Controller and ADC
中文描述： 8051反之亦然混合與LCD控制器和ADC的微控制器
文件頁數(shù)： 6/55頁
文件大?。?/td> 2395K
代理商： VMX51C900
VMX51C900
_______________________________________________________________________________________________
www.ramtron.com
page 6 of 55
Instruction Set
The following tables describe the instruction set of the
VMX51C900. The instructions are function and binary code
compatible with industry standard 8051s.
T
ABLE
4:
L
EGEND FOR
I
NSTRUCTION
S
ET
T
ABLE
Symbol
A
Rn
Direct
@Ri
rel
bit
#data
#data 16
addr 16
addr 11
Function
Accumulator
Register R0-R7
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two's complement offset byte
Direct bit address
8-bit constant
16-bit constant
16-bit destination address
11-bit destination address
T
ABLE
5:
VRS570/VRS580
I
NSTRUCTION
S
ET
Mnemonic
Description
Size
(bytes)
Instr.
Cycles
Op-
Code
Arithmetic instructions
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
Logical Instructions
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data
CLR A
CPL A
SWAP A
RL A
RLC A
RR A
RRC A
Add register to A
Add direct byte to A
Add data memory to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add data memory to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract data mem from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment data memory
Decrement A
Decrement register
Decrement direct byte
Decrement data memory
Increment data pointer
Multiply A by B
Divide A by B
Decimal adjust A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
28h-2Fh
25h
26h,27h
24h
38h-3Fh
35h
36h,37h
34h
98h-9Fh
95h
96h-97h
94h
04h
08h-0Fh
05h
06h, 07h
14h
18h-1Fh
15h
16h,17h
A3h
A4h
84h
D4h
AND register to A
AND direct byte to A
AND data memory to A
AND immediate to A
AND A to direct byte
AND immediate data to direct byte
OR register to A
OR direct byte to A
OR data memory to A
OR immediate to A
OR A to direct byte
OR immediate data to direct byte
Exclusive-OR register to A
Exclusive-OR direct byte to A
Exclusive-OR data memory to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate to direct byte
Clear A
Compliment A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
58h-5Fh
55h
56-57h
54h
52h
53h
48h-4Fh
45h
46h,47h
44h
42h
43h
68h-6Fh
65h
66h,67h
64h
62h
63h
E4h
F4h
C4h
23h
33h
03h
13h
Mnemonic
Description
Size
(bytes)
Instr.
Cycles
Op
Code
Boolean Instruction
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
ANL C,bit
ANL C,#bit
ORL C,bit
ORL C,#bit
MOV C,bit
MOV bit,C
Data Transfer Instructions
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX A, @DPTR
MOVX @Ri, A
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
Branching Instructions
Clear Carry bit
Clear bit
Set Carry bit to 1
Set bit to 1
Complement Carry bit
Complement bit
Logical AND between Carry and bit
Logical AND between Carry and not bit
Logical ORL between Carry and bit
Logical ORL between Carry and not bit
Copy bit value into Carry
Copy Carry value into Bit
1
2
1
2
1
2
2
2
2
2
2
2
1
1
1
1
1
1
2
2
2
2
1
2
C3h
C2h
D3h
D2h
B3h
B2h
82h
A0h,B0h
72h
A0h
A2h
92h
Move register to A
Move direct byte to A
Move data memory to A
Move immediate to A
Move A to register
Move direct byte to register
Move immediate to register
Move A to direct byte
Move register to direct byte
Move direct byte to direct byte
Move data memory to direct byte
Move immediate to direct byte
Move A to data memory
Move direct byte to data memory
Move immediate to data memory
Move immediate to data pointer
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (A8) to A
Move external data (A16) to A
Move A to external data (A8)
Move A to external data (A16)
Push direct byte onto stack
Pop direct byte from stack
Exchange A and register
Exchange A and direct byte
Exchange A and data memory
Exchange A and data memory nibble
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
E8h-Efh
E5h
E6h,E7h
74h
F8h-FFh
A8h-AFh
78h-7Fh
F5h
88h-8Fh
85h
86h,87h
75h
F6h,F7h
A6h,A7h
76h-77h
90h
93h
83h
E2h,E3h
E0h
F2h,F3h
F0h
C0h
D0h
C8h-CFh
C5h
C6h,C7h
D6h,D7h
ACALL addr 11
Absolute call to subroutine
2
2
11h,31h,
51h,71h,
91h,B1h,
D1h,F1h
12h
22h
32h
01h,21h,
41h,61h,
81h,A1h,
C1h,E1h
02h
80h
40h
50h
20h
30h
10h
73h
60h
70h
B5h
B4h
B8h-BFh
B6h,B7h
D8h-DFh
D5h
LCALL addr 16
RET
RETI
Long call to subroutine
Return from subroutine
Return from interrupt
3
1
1
2
2
2
AJMP addr 11
Absolute jump unconditional
2
2
LJMP addr 16
SJMP rel
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit,rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A
, direct, rel
CJNE A, #d, rel
CJNE Rn, #d, rel
CJNE @Ri, #d, rel
DJNZ Rn, rel
DJNZ direct, rel
Miscellaneous Instruction
NOP
Long jump unconditional
Short jump (relative address)
Jump on carry = 1
Jump on carry = 0
Jump on direct bit = 1
Jump on direct bit = 0
Jump on direct bit = 1 and clear
Jump indirect relative DPTR
Jump on accumulator = 0
Jump on accumulator 1= 0
Compare A, direct JNE relative
Compare A, immediate JNE relative
Compare reg, immediate JNE relative
Compare ind, immediate JNE relative
Decrement register, JNZ relative
Decrement direct byte, JNZ relative
3
2
2
2
3
3
3
1
2
2
3
3
3
3
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
No operation
1
1
00h,A5h
Rn:
@Ri:
#data:
#data16: Immediate data included with instruction
bit:
address at the bit level
rel:
relative address to Program counter from +127 to –128
Addr11: 11-bit address range
Addr16: 16-bit address range
#d:
Immediate Data supplied with instruction
Any of the register R0 to R7
Indirect addressing using Register R0 or R1
immediate Data provided with Instruction
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VMX51C900-25-L 功能描述:8位微控制器 -MCU 8K+256 25MHz 5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
VMX51C900-25-LG 功能描述:8位微控制器 -MCU 8K+256 25MHz 5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
VMX51C900-25-L-G 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Versa Mix 8051 MCU with LCD Controller and ADC
VMX51C900-25-P 功能描述:8位微控制器 -MCU 8K+256 25MHz 5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
VMX51C900-25-PG 功能描述:8位微控制器 -MCU 8K+256 25MHz 5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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