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| 型號： | VMX51C900 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Versa Mix 8051 MCU with LCD Controller and ADC |
| 中文描述： | 8051反之亦然混合與LCD控制器和ADC的微控制器 |
| 文件頁數(shù)： | 38/55頁 |
| 文件大?。?/td> | 2395K |
| 代理商： | VMX51C900 |
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VMX51C900
______________________________________________________________________________________________
www.ramtron.com
page 38 of 55
Execution of an Interrupt
When the processor receives an interrupt request, an
automatic jump to the desired subroutine occurs. This
jump is similar to executing a branch to a subroutine
instruction: the processor automatically saves the
address of the next instruction on the stack. An internal
flag is set to indicate that an interrupt is taking place,
and then the jump instruction is executed. An interrupt
subroutine must always end with the RETI instruction.
This instruction allows the processor to retrieve the
return address placed on the stack and update the
internal flags of the interrupt controller.
Interrupt Enable and Interrupt Priority
When the VMX51C900 is reset, the IEN0 and IEN1
registers are cleared, disabling all the interrupts. The
corresponding bits in the IEN0 and IEN1 registers must
be set to enable the interrupts.
The IEN0 register is part of the bit addressable internal
RAM. Therefore, each bit can be individually modified
in one instruction without having to modify the other
bits of the register. The IEN1 register that controls the
ADC interrupt is not bit addressable. In order to enable
the ADC interrupt, a direct write must be performed in
the IEN1 register to set the ADCIE bit to 1.
All interrupts can be inhibited by clearing the EA bit of
the IEN0 register.
The priority in which the interrupts are serviced is
displayed in the following table:
T
ABLE
45:
I
NTERRUPT
P
RIORITY
Interrupt Source
RESET + WDT (Highest Priority)
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
ADCIP (Lowest Priority)
Modifying the Order of Priority
The VMX51C900 allows the user to modify the natural
priority of the interrupts by programming the
corresponding bits in the IP (interrupt priority) register.
When any bit in this register is set to 1, it gives the
corresponding source priority over interrupts from
sources that do not have their corresponding IP or IP1
bit set to 1.
The IP and IP1 register structures are represented in
the following tables:
T
ABLE
46:
IP
I
NTERRUPT
P
RIORITY
R
EGISTER
–SFR
B8
H
7
6
5
-
-
PT2
Bit
Mnemonic
7
-
6
-
5
PT2
4
PS
3
PT1
2
PX1
1
PT0
0
PX0
4
PS
3
2
1
0
PT1
PX1
PT0
PX0
Description
Gives Timer 2 Interrupt Higher Priority
Gives Serial Port Interrupt Higher Priority
Gives Timer 1 Interrupt Higher Priority
Gives INT1 Interrupt Higher Priority
Gives Timer 0 Interrupt Higher Priority
Gives INT0 Interrupt Higher Priority
T
ABLE
47:
IP1
I
NTERRUPT
P
RIORITY
R
EGISTER
1
–SFR
B9
H
7
6
5
-
-
-
Bit
Mnemonic
7:4
-
3
ADCIP
2:0
-
4
-
3
2
1
-
0
-
ADCIP
-
Description
Gives ADC Interrupt Higher Priority
External Interrupts
The VMX51C900 has two external interrupt inputs
(INT0 and INT1). These interrupt lines are shared with
P3.2 and P3.3.
The IE0 and IE1 bits of the TCON register are external
flags that detect a low level or high-to-low transition on
the INT0, INT1 interrupt pins respectively. These flags
are automatically cleared when the corresponding
interrupt is serviced.
Bits IT0 and IT1 of the TCON register determine
whether the external interrupts are level or edge
sensitive.
IT0 = 0: The INT0, if enabled, occurs if a low level is
present on P3.2
IT0 = 1: The INT0, if enabled, occurs if a high-to-low
transition is detected on P3.2
IT1 = 0: The INT1, if enabled, occurs if a low level is
present on P3.3
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VMX51C900-25-L | 功能描述:8位微控制器 -MCU 8K+256 25MHz 5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| VMX51C900-25-LG | 功能描述:8位微控制器 -MCU 8K+256 25MHz 5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| VMX51C900-25-L-G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Versa Mix 8051 MCU with LCD Controller and ADC |
| VMX51C900-25-P | 功能描述:8位微控制器 -MCU 8K+256 25MHz 5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| VMX51C900-25-PG | 功能描述:8位微控制器 -MCU 8K+256 25MHz 5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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