參數(shù)資料
型號： V58C2256324SAH-36
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 8M X 32 DDR DRAM, 0.55 ns, PBGA144
封裝： ROHS COMPLIANT, BGA-144
文件頁數(shù)： 8/37頁
文件大?。?/td> 370K
代理商： V58C2256324SAH-36
16
V58C2256324SA Rev. 1.4 August 2007
ProMOS TECHNOLOGIES
V58C2256324SA
Burst Read Operation: (READ)
The Burst Read operation is initiated by issuing a READ command at the rising edge of the clock after tRCD from the bank activation.
The address inputs (A7.. A0) determine the starting address for the burst. The burst length (2, 4 or 8) must be defined in the Mode
Register. The first data after the READ command is available depending on the CAS latency. The subsequent data is clocked out on
the rising and falling edge of DQSx until the burst is completed. The DQSx signal is generated by the DDR SDRAM during Burst Read
Operations.
Burst Read Operation
CLK
Read
Command
NOP
Burst length = 4
DQSx
DQx
D-out
0
D-out
1
D-out
2
D-out
3
CAS latency = 3
CL = 3
Read
Preamble
Read
Postamble
DQSx
DQx
CAS latency = 4
CL = 4
D-out
0
D-out
1
D-out
2
D-out
3
Read
Preamble
Read
Postamble
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