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參數(shù)資料
| 型號： | V58C2256324SAH-36 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.55 ns, PBGA144 |
| 封裝： | ROHS COMPLIANT, BGA-144 |
| 文件頁數(shù)： | 2/37頁 |
| 文件大小： | 370K |
| 代理商： | V58C2256324SAH-36 |
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10
V58C2256324SA Rev. 1.4 August 2007
ProMOS TECHNOLOGIES
V58C2256324SA
Power-Up Sequence
The f ollowing sequence is high ly rec omm ended f or Power -Up:
1. Apply power and start clock. Maint ain CKE and t he ot her pins are in NOP conditions at the input
2. Apply VDD bef ore or at the s ame time as VDDQ
, apply VDDQ bef ore or at the sam e time as VREF , VTT
3. Start clock , maint ain st able conditions for 200 mins
4. Apply NOP and set CKE to high
5. Apply a Prechar ge All command
6. Issue EMRS (ext ended m ode r egi ster set ) command to enable the DLL
7. Issue a Mode Register Set command f or DLL r eset 200 cycles of cloc k input are requi red t o lock the DLL.
8. Issue Prechar ge comm ands f or all banks of the device.
9. Issue two or more Auto-Refresh commands.
10. Issue a Mod e Register Set comm and. (This step may also be taken as step 6)
Power Up Sequence
Mode Register Set Timing
The DDR SDRAM should be act ivat ed wit h CK E already high prior to writing into the mode register. Two c loc k c ycles are required
complete the w rite operation in the mode register. The mo de register content s can be changed using the sam e com mand and clock cycl
requirements during operat ion as long as all banks are in t he idle st ate.
Mode Regist er Set Timing
Cloc k
Comm and
EMRS
PREA
DLL
PREA
ARef
MRS
LP
EMRS
t
MRD
200 Cloc k min.
t
RP
t
RFC
t
RFC
t
MRD
t
RP
NOP
2 Clock
mi n.
Reset
Clk
Comm and
t
RP
tMRD
NOP
PREA
NOP
MRS
NOP
Comm.
any
NOP
11. Issue a Low Power Extended Mode Register Set Command (L-device only).
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