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參數(shù)資料
| 型號： | V58C2256324SAH-36 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.55 ns, PBGA144 |
| 封裝： | ROHS COMPLIANT, BGA-144 |
| 文件頁數(shù)： | 1/37頁 |
| 文件大?。?/td> | 370K |
| 代理商： | V58C2256324SAH-36 |
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V58C2256324SA
HIGH PERFORMANCE LOW POWER
2.5 VOLT 8M X 32 DDR SDRAM
4 BANKS X 2M X 32
V58C2256324SA Rev. 1.4 August 2007
28
33
36
4A
4
5
System Frequency (fCK)
350 MHz
300 MHz
275 MHz
250 MHz
200 MHz
Clock Cycle Time (tCK3)
4.0
5.0
Clock Cycle Time (tCK4)
3.3
3.6
4.0
5.0
Clock Cycle Time (tCK5)
2.85
3.3
3.6
4.0
5.0
Features
■ 4 banks x 2M x 32 organization
■ High speed data transfer rates with system frequency
up to 350 MHz
■ Data Mask for Write Control (DM)
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 3, 4, 5
■ Programmable Wrap Sequence: Sequential
or Interleave
■ Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■ Automatic and Controlled Precharge Command
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 4096 cycles/32ms
■ Available in 144-ball BGA
■ Double Data Rate (DDR)
■ Bidirectional Data Strobe (DQs) for input and output
data, active on both edges
■ On-Chip DLL aligns DQ and DQs transitions with CLK
transitions
■ Differential clock inputs CLK and /CLK
■ Power Supply 2.5V ± 0.2V
■ 2.5V SSTL2 Weak Mode interface(Z0=34 ohm)
■ 1.8V Matched Impedance Interface (Z0=60 ohm)
Description
The V58C2256324SA is a four bank DDR DRAM
organized as 4 banks x 2M x 32. The V58C2256324SA
achieves high speed data transfer rates by employing a
chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are possible on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device
.
Device Usage Chart
Operating
Temperature
Range
Package Outline
CLK Cycle Time (ns)
Power
Temperature
Mark
144-ball BGA
-28
-33
-36
-4A
-4
-5
Std.
L
0°C to 70°C
Blank
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