參數(shù)資料
型號(hào)： V58C2256324SAH-36
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 8M X 32 DDR DRAM, 0.55 ns, PBGA144
封裝： ROHS COMPLIANT, BGA-144
文件頁(yè)數(shù)： 33/37頁(yè)
文件大?。?/td> 370K
代理商： V58C2256324SAH-36
5
V58C2256324SA Rev. 1.4 August 2007
ProMOS TECHNOLOGIES
V58C2256324SA
Mode Register Set
The mode register stores the data for controlling the various operating modes of the DDR SDRAM. It programs CAS latency, addressing
mode, burst length, test mode, DLL ON and various vendor specific options. The default value of the mode register is not defined.
Therefore the mode register must be written after power up to operate the DDR SDRAM. The DDR SDRAM should be activated with
CKE already high prior to writing into the Mode Register. The Mode Register is written by using the MRS command. The state of the
address signals registered in the same cycle as MRS command is written in the mode register. The value can be changed as long as
all banks are in the idle state.
The mode register is divided into various fields depending on functionality. The burst length uses A2.. A0, CAS latency (read latency
from column address) uses A6.. A4. A7 is used for test mode, A8 is used for DLL Reset. A7, A8 and BA1 must be set to low for normal
DDR SDRAM operation. A9.. A11 is reserved for future use. BA0 selects Extended Mode Register Setup operation when set to 1. Refer
to the table for specific codes for various burst length, addressing modes and CAS latencies.
Mode Register Bitmap
BA1
BA0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DLL
RFU
TM
CAS Latency
BT
Burst Length
A7
0
1
mode
Normal
Testmode
A8
0
1
DLL Reset
Yes
DLL Reset
No
A3
0
1
Type
Sequential
Burst Type
Address Bus
Mode Register
Latency
3
A6
A5
A4
All other Reserved
4
0
1
0
CAS Latency
Length
2
A2
A1
A0
4
8
0
1
Sequential
Interleave
0
8
4
2
Burst Length
All other Reserved
BA0
0
1
Accessed Register
Extend. Mode Reg.
Extended Mode
Register Access
Mode Register
00
A11
A10
RFU
0
5
1
0
Interleave
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