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參數(shù)資料
| 型號(hào)： | V58C2256324SAH-36 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.55 ns, PBGA144 |
| 封裝： | ROHS COMPLIANT, BGA-144 |
| 文件頁數(shù)： | 21/37頁 |
| 文件大?。?/td> | 370K |
| 代理商： | V58C2256324SAH-36 |
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V58C2256324SA Rev. 1.4 August 2007
ProMOS TECHNOLOGIES
V58C2256324SA
Note: All entries assume the CKE was High during the preceding clock cycle
Note: 1. Illegal to bank specified states; function may be legal in the bank indicated by BAx, depending on the state of that bank
Note: 2. Must satisfy bus contention, bus turn around, write recovery requirements.
Note: 3. If both banks are idle, and CKE is inactive, the device will enter Power Down Mode. All input buffers except CKE, CLK and
CLK# will be disabled.
Note: 4. If both banks are idle, and CKE is deactivated coincidentally with an AutoRefresh command, the device will enter SelfRefresh
Mode. All input buffers except CKE will be disabled.
Note: 5. Illegal, if tRRD is not satisfied.
Note: 6. Illegal, if tRAS is not satisfied.
Note: 7. Must satisfy burst interrupt condition.
Note: 8. Must mask two preceding data bits with the DM pin.
Note: 9. Illegal, if tRCD is not satisfied.
Note: 10. Illegal, if tWR is not satisfied.
Note: 11. Illegal, if tRC is not satisfied.
Abbreviations:
H
High Level
L
Low Level
X
DontCare
V
Valid Data Input
RA
Row Address
BA
Bank Address
PA
Precharge All
NOP
No Operation
CA
Column Address
Ax
Address Line x
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