參數(shù)資料
型號： UPD784218YGC
廠商： NEC Corp.
英文描述： Cable; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No
中文描述： 16-/8-bit的單晶片微控制器
文件頁數(shù)： 68/92頁
文件大?。?/td> 617K
代理商： UPD784218YGC
μ
PD784218, 784218Y
Data Sheet U12304EJ2V0DS00
68
AC Characteristics (T
A
= –40 to +85
°
C, V
DD
= AV
DD
= 2.2 to 5.5 V, V
SS
= AV
SS
= 0 V)
(1) Read/write operation (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Cycle time
t
CYK
4.5 V
≤
V
DD
≤
5.5 V
80
ns
2.7 V
≤
V
DD
< 4.5 V
160
ns
2.2 V
≤
V
DD
< 2.7 V
320
ns
Address setup time (to ASTB
↓
)
t
SAST
V
DD
= 5.0 V
(0.5 + a) T – 11
ns
V
DD
= 3.0 V
(0.5 + a) T – 15
ns
Address hold time (from ASTB
↓
)
t
HSTLA
V
DD
= 5.0 V
0.5T – 19
ns
V
DD
= 3.0 V
0.5T – 24
ns
ASTB high-level width
t
WSTH
V
DD
= 5.0 V
(0.5 + a) T – 17
ns
V
DD
= 3.0 V
(0.5 + a) T – 40
ns
Address hold time (from RD
↑
)
t
HRA
V
DD
= 5.0 V
0.5T – 14
ns
V
DD
= 3.0 V
0.5T – 14
ns
Delay time from address to RD
↓
t
DAR
V
DD
= 5.0 V
(1 + a) T – 24
ns
V
DD
= 3.0 V
(1 + a) T – 24
ns
Address float time (from RD
↓
)
t
FRA
0
ns
Data input time from address
t
DAID
V
DD
= 5.0 V
(2.5 + a + n) T – 37
ns
V
DD
= 3.0 V
(2.5 + a + n) T – 52
ns
Data input time from ASTB
↓
t
DSTID
V
DD
= 5.0 V
(2 + n) T – 35
ns
V
DD
= 3.0 V
(2 + n) T – 50
ns
Data input time from RD
↓
t
DRID
V
DD
= 5.0 V
(1.5 + n) T – 40
ns
V
DD
= 3.0 V
(1.5 + n) T – 50
ns
Delay time from ASTB
↓
to RD
↓
t
DSTR
V
DD
= 5.0 V
0.5T – 9
ns
V
DD
= 3.0 V
0.5T – 9
ns
Data hold time (from RD
↑
)
t
HRID
0
ns
Address active time from RD
↑
t
DRA
V
DD
= 5.0 V
0.5T – 2
ns
V
DD
= 3.0 V
0.5T – 12
ns
Delay time from RD
↑
to ASTB
↑
t
DRST
V
DD
= 5.0 V
0.5T – 9
ns
V
DD
= 3.0 V
0.5T – 9
ns
RD low-level width
t
WRL
V
DD
= 5.0 V
(1.5 + n) T – 25
ns
V
DD
= 3.0 V
(1.5 + n) T – 30
ns
Delay time from address to WR
↓
t
DAW
V
DD
= 5.0 V
(1 + a) T – 24
ns
V
DD
= 3.0 V
(1 + a) T – 24
ns
Address hold time (from WR
↑
)
t
HWA
V
DD
= 5.0 V
0.5T – 14
ns
V
DD
= 3.0 V
0.5T – 14
ns
Delay time from ASTB
↓
to data
output
t
DSTOD
V
DD
= 5.0 V
0.5T + 15
ns
V
DD
= 3.0 V
0.5T + 20
ns
Remark
T: t
CYK
= 1/f
XX
(f
XX
: main system clock frequency)
a: 1 (during address wait), otherwise 0
n: Number of waits (n
≥
0)
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