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參數(shù)資料
| 型號： | UPD784218YGC |
| 廠商： | NEC Corp. |
| 英文描述： | Cable; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No |
| 中文描述： | 16-/8-bit的單晶片微控制器 |
| 文件頁數(shù)： | 47/92頁 |
| 文件大小： | 617K |
| 代理商： | UPD784218YGC |
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μ
PD784218, 784218Y
Data Sheet U12304EJ2V0DS00
47
Table 9-2. Interrupt Sources (2/2)
Type
Default
Priority
Source
Internal/
External
Macro
Service
Name
Trigger
Maskable
10
INTSR1
End of UART reception by ASI1
Internal
√
INTCSI1
INTST1
End of 3-wire transfer by CSI1
End of UART transmission by ASI1
11
12
INTSER2
Occurrence of UART reception error in ASI2
13
INTSR2
INTCSI2
End of UART reception by ASI2
End of 3-wire transfer by CSI2
14
15
INTST2
INTTM3
End of UART transmission by ASI2
Reference time interval signal from watch timer
16
INTTM00
Signal indicating coincidence between 16-bit
timer counter and capture/compare register
(CR00)
Signal indicating coincidence between 16-bit
timer counter and capture/compare register
(CR01)
17
INTTM01
18
INTTM1
Occurrence of coincidence signal of 8-bit
timer/event counter 1
19
INTTM2
Occurrence of coincidence signal of 8-bit
timer/event counter 2
20
21
INTAD
INTTM5
End of conversion by A/D converter
Occurrence of coincidence signal of 8-bit
timer/event counter 5
22
INTTM6
Occurrence of coincidence signal of 8-bit
timer/event counter 6
23
INTTM7
Occurrence of coincidence signal of 8-bit
timer/event counter 7
24
INTTM8
Occurrence of coincidence signal of 8-bit
timer/event counter 8
25
INTWT
Overflow of watch timer
26
(lowest)
INTKR
Detection of falling edge of port 8
External
Remarks 1.
ASI: Asynchronous Serial Interface
CSI: Clocked Serial Interface
2.
Two watchdog timer interrupt sources, non-maskable interrupt (INTWDT) and maskable interrupt
(INTWDTM), are available and only one of those can be selected.
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